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K7A161801A Datasheet(PDF) 3 Page - Samsung semiconductor |
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K7A161801A Datasheet(HTML) 3 Page - Samsung semiconductor |
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3 / 19 page  K7B161825A 512Kx36 & 1Mx18 Synchronous SRAM - 3 - Rev 2.0 Nov. 2003 K7B163625A 512Kx36 & 1Mx18-Bit Synchronous Burst SRAM The K7B163625A and K7B161825A are 18,874,368-bit Syn- chronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(32/18) bits and inte- grates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is per- formed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status pro- cessor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system ′s burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by cur- rent regardless of CLK. The K7B163625A and K7B161825A are fabricated using SAM- SUNG ′s high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce. GENERAL DESCRIPTION FEATURES LOGIC BLOCK DIAGRAM • Synchronous Operation. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O • 5V Tolerant Inputs Except I/O Pins. • Byte Writable Function. • Global Write Enable Controls a full bus-width write. • Power Down State via ZZ Signal. • LBO Pin allows a choice of either a interleaved burst or a lin- ear burst. • Three Chip Enables for simple depth expansion with No Data Contention only for TQFP. • Asynchronous Output Enable Control. • ADSP , ADSC, ADV Burst Control Pins. • TTL-Level Three-State Output. • 100-TQFP-1420A • Operating in commeical and industrial temperature range. CLK LBO ADV ADSC ADSP CS1 CS2 CS2 GW BW WEx OE ZZ DQa0 ~ DQd7 or DQa0 ~ DQb7 BURST CONTROL LOGIC BURST 512Kx36, 1Mx18 ADDRESS CONTROL DATA-IN ADDRESS COUNTER MEMORY ARRAY REGISTER REGISTER LOGIC A ′0~A′1 A0~A1 or A2~A19 or A0~A19 DQPa ~ DQPd A0~A18 A2~A18 (x=a,b,c,d or a,b) DQPa,DQPb OUTPUT BUFFER FAST ACCESS TIMES PARAMETER Symbol -75 -85 Unit Cycle Time tCYC 8.5 10 ns Clock Access Time tCD 7.5 8.5 ns Output Enable Access Time tOE 3.5 4.0 ns |
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