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K7R163684B Datasheet(PDF) 7 Page - Samsung semiconductor |
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K7R163684B Datasheet(HTML) 7 Page - Samsung semiconductor |
7 / 18 page - 7 - Rev 3.1 July. 2004 512Kx36 & 1Mx18 QDRTM II b4 SRAM K7R163684B K7R161884B STATE DIAGRAM Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1. 2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are the same case. 3. Read and write state machine can be active simulateneously. 4. State machine control timing sequence is controlled by K. READ DDR READ D count=D count+1 POWER-UP WRITE NOP LOAD NEW READ ADDRESS D count=0 ALWAYS WRITE ALWAYS READ WRITE READ D count=2 INCREMENT READ ADDRESS READ NOP INCREMENT WRITE ADDRESS DDR WRITE D count=D count+1 LOAD NEW WRITE ADDRESS D count=0 ALWAYS READ D count=1 READ D count=2 ALWAYS WRITE D count=2 WRITE D count=1 WRITE D count=2 |
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