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ISP1362BD Datasheet(PDF) 11 Page - NXP Semiconductors |
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ISP1362BD Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 150 page Philips Semiconductors ISP1362 Single-chip USB OTG controller Product data Rev. 03 — 06 January 2004 11 of 150 9397 750 12337 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. H_PSW2 36 G9 O connects to the external PMOS switch LOW — switches ON the PMOS providing VBUS to the downstream port HIGH — switches OFF the PMOS when not in use, leave this pin open open-drain output DGND 37 G10 - digital ground CLKOUT 38 F9 O programmable clock output; the default clock frequency is 12 MHz and can be varied from 3 MHz to 48 MHz push-pull output GL 39 F10 O GoodLink LED indicator output; the LED is OFF by default, blinks ON upon USB traffic open-drain output; 4 mA VCC 40 E9 - supply voltage (3.3 V); it is recommended to connect a decoupling capacitor of 0.01 µF H_OC2 41 E10 I overcurrent sense input for downstream port 2; both the digital and analog overcurrent inputs can be used for port 2, depending on the hardware mode register setting; when not in use, it is recommended to connect this pin to the VDD_5V pin H_OC1 42 D9 I overcurrent sensing input for downstream port 1; both the digital and analog overcurrent inputs can be used for port 1, depending on the hardware mode register setting; when not in use, it is recommended to connect this pin to the VDD_5V pin X1 43 D10 AI crystal input; connected directly to a 12 MHz crystal; when this pin is connected to an external clock oscillator, leave pin X2 open X2 44 C9 AO crystal output; connected directly to a 12 MHz crystal; when pin X1 is connected to an external clock oscillator, leave this pin open OTGMODE 45 C10 I to select whether port 1 is operating in the OTG or non-OTG mode; see Table 8 input with hysteresis H_DM2 46 B9 AI/O downstream D − signal; host only, port 2; when not in use, leave this pin open and set bit ConnectPullDown_DS2 of the HcHardwareConfiguration register H_DP2 47 B10 AI/O downstream D+ signal; host only, port 2; when not in use, leave this pin open and set bit ConnectPullDown_DS2 of the HcHardwareConfiguration register ID 48 A10 I input pin for sensing OTG ID; the status of this input pin is reflected in the OTGStatus register (bit 0); see Table 8 input with hysteresis OTG_DM1 49 A9 AI/O D − signal of the OTG port, the downstream host port 1 or the upstream device port; when not in use, leave this pin open and set bit ConnectPullDown_DS1 of the HcHardwareConfiguration register[3] OTG_DP1 50 B8 AI/O D + signal of the OTG port, the downstream host port 1 or the upstream device port; when not in use, leave this pin open and set bit ConnectPullDown_DS1 of the HcHardwareConfiguration register[3] Table 2: Pin description…continued Symbol[1] Pin LQFP64 Ball TFBGA64 Type[2] Description |
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