6.42

5

IDT71V016, 3.3V CMOS Static RAM

1 Meg (64K x 16-Bit)

Commercial and Industrial Temperature Ranges

PAR

T IN

OBSOLESCENCE

ORDER

71V016SA

FOR

NEW

DESIGNS

71V016S15

71V016S20

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

READ CYCLE

Read Cycle Time

15

____

20

____

ns

Address Access Time

____

15

____

20

ns

Chip Select Access Time

____

15

____

20

ns

Chip Select Low to Output in Low-Z

5

____

5

____

ns

Chip Select High to Output in High-Z

____

6

____

8ns

Output Enable Low to Output Valid

____

8

____

10

ns

Output Enable Low to Output in Low-Z

0

____

0

____

ns

Output Enable High to Output in High-Z

____

6

____

8ns

Output Hold from Address Change

4

—

5

—

ns

Byte Enable Low to Output Valid

—

8

____

10

ns

Byte Enable Low to Output in Low-Z

0

____

0

____

ns

Byte Enable High to Output in High-Z

____

6

____

8ns

WRITE CYCLE

Write Cycle Time

15

____

20

____

ns

Address Valid to End of Write

10

____

12

____

ns

Chip Select Low to End of Write

10

____

12

____

ns

Byte Enable Low to End of Write

10

____

12

____

ns

Address Set-up Time

0

____

0

____

ns

Address Hold from End of Write

0

____

0

____

ns

Write Pulse Width

10

____

12

____

ns

Data Valid to End of Write

8

____

10

____

ns

Data Hold Time

0

____

0

____

ns

Write Enable High to Output in Low-Z

1

____

1

____

ns

Write Enable Low to Output in High-Z

____

6

____

8ns

3211 tbl 10

NOTES:

1.

WE is HIGH for Read Cycle.

2. Device is continuously selected,

CS isLOW.

3.

OE, BHE, and BLE are LOW.

ADDRESS

3211 drw 07

NOTE:

1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.