ú

û

ù

ê

ë

é

+

+

=

2

1

)

(

(min)

(min)

//

2

L

L

ON

DS

OUT

OUT

IN

DCR

DCR

R

I

V

V

L

PSM

load

I

I

D

=

)

(

TPS62184

SLVSCQ5A – DECEMBER 2014 – REVISED FEBRUARY 2015

www.ti.com

Device Functional Modes (continued)

space

If the load decreases to very light loads and only one phase is needed, either phase (master or follower) might

be active. The load current level at which Power Save Mode is entered is calculated as follows:

spacing

(5)

spacing

Equation 7 is used to calculate

8.4.3 Minimum Duty Cycle and 100% Mode Operation

When the input voltage comes close to the output voltage, the device enters 100% mode and both high-side

output voltage regulation is calculated as:

spacing

(6)

spacing

This allows the conversion of small input to output voltage differences, for example for longest operation time in

battery powered applications. In 100% duty cycle mode, the low-side FET is switched off.

While the maximum ON-time is not limited, the AEE feature, explained in the next section, secures a minimum

ON-time of about 100 ns.

8.4.4 Automatic Efficiency Enhancement (AEE™)

AEE™ provides highest efficiency over the entire input voltage and output voltage range by automatically

adjusting the converter's switching frequency. This is achieved by setting the predictive off-time of the converter.

The efficiency of a switched mode converter is determined by the power losses during the conversion. The

following equation shows the relation between the inductor ripple current, switching frequency and duty cycle.

spacing

10

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