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SN65HVD73DGSR Datasheet(PDF) 7 Page - Texas Instruments |
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SN65HVD73DGSR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 41 page SN65HVD70, SN65HVD71, SN65HVD73, SN65HVD74, SN65HVD76, SN65HVD77 www.ti.com SLLSEI9E – MAY 2014 – REVISED OCTOBER 2014 7.4 Thermal Information — D Packages THERMAL METRIC D D Unit (8 PINS) (14 PINS) RθJA Junction-to-ambient thermal resistance 110.7 83.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 54.7 42.9 RθJB Junction-to-board thermal resistance 51.3 37.8 ψJT Junction-to-top characterization parameter 9.2 9.3 ψJB Junction-to-board characterization parameter 50.7 37.5 TJ(TSD) Thermal shut-down junction temperature 170 °C 7.5 Thermal Information — DGS and DGK Packages THERMAL METRIC DGS DGK Unit (10 PINS) (8 PINS) RθJA Junction-to-ambient thermal resistance 165.5 168.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 37.7 62.2 RθJB Junction-to-board thermal resistance 86.4 89.5 ψJT Junction-to-top characterization parameter 1.4 7.4 ψJB Junction-to-board characterization parameter 84.8 87.9 TJ(TSD) Thermal shut-down junction temperature 170 °C 7.6 Power Dissipation PARAMETER TEST CONDITIONS VALUE UNITS HVD70, HVD71 150 RL = 300 Ω, Unterminated HVD73, HVD74 180 mW CL = 50 pF (driver) Power Dissipation HVD76, HVD77 220 driver and receiver enabled, VCC = 3.6 V, TJ = 150°C HVD70, HVD71 190 50% duty cycle square-wave signal at RL = 100 Ω, PD RS-422 load HVD73, HVD74 220 mW signaling rate: CL = 50 pF (driver) • HVD70 and HVD71 at 400 kbps HVD76, HVD77 250 • HVD73 and HVD74 at 20 Mbps HVD70, HVD71 230 • HVD76 and HVD77 at 50 Mbps RL = 54 Ω, RS-485 load HVD73, HVD74 255 mW CL = 50 pF (driver) HVD76, HVD77 285 7.7 Electrical Characteristics over recommended operating range (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RL = 60 Ω, 375 Ω on each 1.5 2 V output to –7 V to 12 V, See Figure 15 |VOD| Driver differential output voltage magnitude RL = 54 Ω (RS-485), See Figure 16 1.5 2 V RL = 100 Ω (RS-422) TJ ≥ 0°C, 2 V VCC ≥ 3.2 V, See Figure 16 Change in magnitude of driver differential output Δ|VOD| RL = 54 Ω, CL = 50 pF, See Figure 16 –50 0 50 mV voltage VOC(SS) Steady-state common-mode output voltage 1 VCC / 2 3 V Change in differential driver output common-mode ΔVOC Center of two 27- Ω load resistors, See Figure 16 –50 0 50 mV voltage VOC(PP) Peak-to-peak driver common-mode output voltage 500 mV COD Differential output capacitance 15 pF Positive-going receiver differential input voltage VIT+ See (1) -70 –20 mV threshold Negative-going receiver differential input voltage VIT– –200 -140 See (1) mV threshold Receiver differential input voltage threshold hysteresis Vhys 40 70 mV (VIT+ – VIT–) (1) Under any specific conditions, VIT+ is assured to be at least Vhys higher than VIT–. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: SN65HVD70 SN65HVD71 SN65HVD73 SN65HVD74 SN65HVD76 SN65HVD77 |
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