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TPS55340-Q1 Datasheet(PDF) 10 Page - Texas Instruments

Part # TPS55340-Q1
Description  Integrated 5-A, Wide Input Range Boost, SEPIC, or Flyback DC-DC Converter
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS55340-Q1 Datasheet(HTML) 10 Page - Texas Instruments

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TPS55340-Q1
SLVSBV5A – JUNE 2014 – REVISED JULY 2016
www.ti.com
Product Folder Links: TPS55340-Q1
Submit Documentation Feedback
Copyright © 2014–2016, Texas Instruments Incorporated
Feature Description (continued)
A ramp signal from the oscillator is added to the inductor current ramp to provide slope compensation. Slope
compensation is required to avoid sub-harmonic oscillation that is intrinsic to peak-current mode control at duty
cycles higher than 50%. If the inductor value is too small, the internal slope compensation may not be adequate
to maintain stability.
The PWM control feedback loop regulates the FB pin to a reference voltage through a transconductance error
amplifier. The output of the error amplifier is connected to the COMP pin. An external RC-compensation network
connected to the COMP pin is chosen for feedback loop stability and optimum transient response.
7.3.2 Switching Frequency
The switching frequency is set by a resistor (R(FREQ)) connected to the FREQ pin of the TPS55340-Q1 device.
The relationship between the resistance of R(FREQ) and frequency is shown in the Figure 5. Do not leave this pin
open. A resistor must always be connected from the FREQ pin to ground for proper operation. Use Equation 1 to
calculate the resistor value required for a desired frequency.
R(FREQ) (kΩ) = 57500 × ƒS
–1.03 (kHz)
(1)
For the given resistor value, use Equation 2 to calculate the corresponding frequency.
ƒS (kHz) = 41600 × R(FREQ)
–0.97 (kΩ)
(2)
The TPS55340-Q1 switching frequency can synchronized to an external clock signal that is applied to the SYNC
pin. The required logic levels of the external clock are shown in the Electrical Characteristics table. The
recommended duty cycle of the clock is in the range of 10% to 90%. A resistor must be connected from the
FREQ pin to ground when the converter is synchronized to the external clock and the external clock frequency
must be within ±20% of the corresponding frequency set by the resistor. For example, if the frequency
programmed by the FREQ pin resistor is 600 kHz, the external clock signal must be in the range of 480 to 720
kHz.
With a switching frequency below 280 kHz (typical) after the TPS55340-Q1 enters frequency foldback as
described in the Overcurrent Protection and Frequency Foldback section, if a load remains when the overcurrent
condition is removed the output may not recover to the set value. For the output to return to the set value the
load must be removed completely or the TPS55340-Q1 power cycled with the EN pin or VIN pin. Select a
nominal switching frequency of 350 kHz for quicker recovery from frequency foldback.
When setting the switching frequency higher than 1.2 MHz, TI recommends using an external synchronous clock
as the switching frequency to ensure that the pulse-skipping function works at a light load. When using the
internal switching frequency above 1.2 MHz, the TPS55340-Q1 device might not pulse skip as described in the
Minimum On Time and Pulse Skipping section. When the pulse-skipping function does not work at light loads,
the TPS55340-Q1 device always operates in PWM mode with a minimum ON pulse width. This causes the
output voltage to be higher than the set value with the resistor divider at the FB pin. This occurs in minimum duty
cycle conditions such as when there is light output load or when the input voltage is close to the set output
voltage in a boost topology. In the light load condition a minimum output load will keep the output voltage at the
set value in a boost topology. The minimum load needed can be estimated with Equation 3 or Equation 4 using
the maximum minimum on time of 107 ns and a parasitic C(SW) capacitance of 150 pF. For example when
boosting 5 V to 12 V with 2.5 MHz switching frequency and 2-µH inductor the worst case minimum output load is
36 mA.
when VO – VI < VI
(3)
when VO – VI > VI
(4)


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