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TPS54910PWPG4 Datasheet(PDF) 3 Page - Texas Instruments

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Part # TPS54910PWPG4
Description  3-V TO 4-V INPUT, 9-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS54910PWPG4 Datasheet(HTML) 3 Page - Texas Instruments

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TPS54910
SLVS421C − MARCH 2002 − REVISED FEBRUARY 2005
www.ti.com
3
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VI = 3 V to 4 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
3.0
4.0
V
fs = 350 kHz, SYNC ≤ 0.8 V, RT open,
PH pin open
9.8
17.0
I(Q)
Quiescent current
fs = 550 kHz, SYNC ≥ 2.5 V, RT open,
PH pin open
14.0
23.0
mA
Shutdown, SS/ENA = 0 V
1
1.4
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
2.95
3.0
V
Stop threshold voltage, UVLO
2.70
2.80
V
Hysteresis voltage, UVLO
0.14
0.16
V
Rising and falling edge deglitch, UVLO(1)
2.5
µs
BIAS VOLTAGE
Output voltage, VBIAS
I(VBIAS) = 0
2.70
2.80
2.90
V
Output current, VBIAS (2)
100
µA
CUMULATIVE REFERENCE
Vref
Accuracy
0.882
0.891
0.900
V
REGULATION
Line regulation(1)(3)
IL = 4.5 A, fs = 350 kHz, TJ = 85°C
0.07
%/V
Line regulation(1)(3)
IL = 4.5 A, fs = 550 kHz, TJ = 85°C
0.07
%/V
Load regulation(1)(3)
IL = 0 A to 9 A, fs = 350 kHz, TJ = 85°C
0.03
%/A
Load regulation(1)(3)
IL = 0 A to 9 A, fs = 550 kHz, TJ = 85°C
0.03
%/A
OSCILLATOR
Internally set free running frequency
SYNC ≤ 0.8 V, RT open
280
350
420
kHz
Internally set—free running frequency
SYNC ≥ 2.5 V, RT open
440
550
660
kHz
RT = 180 kΩ (1% resistor to AGND)
252
280
308
Externally set—free running frequency range
RT = 100 kΩ (1% resistor to AGND)
460
500
540
kHz
Externally set free running frequency range
RT = 68 kΩ (1% resistor to AGND)
663
700
762
kHz
High level threshold, SYNC
2.5
V
Low level threshold, SYNC
0.8
V
Pulse duration, external synchronization,
SYNC(1)
50
ns
Frequency range, SYNC(1)
330
700
kHz
Ramp valley(1)
0.75
V
Ramp amplitude (peak-to-peak)(1)
1
V
Minimum controllable on time(1)
200
ns
Maximum duty cycle(1)
90%
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 10


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