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TPS54372PWP Datasheet(PDF) 9 Page - Texas Instruments |
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TPS54372PWP Datasheet(HTML) 9 Page - Texas Instruments |
9 / 21 page www.ti.com OPERATING FREQUENCY R + 500 kHz Switching Frequency 100 [kW] OUTPUT FILTER PCB LAYOUT LAYOUT CONSIDERATIONS FOR THERMAL TPS54372 SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005 separate wide trace for the analog ground signal path. This analog ground should be used for the In the application circuit, RT is grounded through a voltage set-point divider, timing resistor RT, and bias 71.5-k Ω resistor to select the operating frequency of capacitor grounds. Connect this trace directly to 700 kHz. To set a different frequency, place a 68-k Ω AGND (pin 1). to 180-k Ω resistor between RT (pin 20) and analog ground or leave RT floating to select the default of The PH pins should be tied together and routed to 350 kHz. The resistance can be approximated using the output inductor. Because the PH connection is the following equation: the switching node, the inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor The output filter is composed of a 1.0-µH inductor close to the IC and minimize the conductor trace and two 150-µF capacitors. The inductor is a low dc lengths. Connect the output filter capacitor(s) as resistance (0.010 Ω) type, Vishay IHLP-2525CZ-01 shown, between the VOUT trace and PGND. It is 1.0-µH, 8.5-A rated dc output. The capacitors used important to keep the loop formed by the PH pins, are 150-µF, 6.3-V special polymer types. Lout, Cout, and PGND as small as practical. Place the compensation components from the VOUT trace to the VSENSE and COMP pins. Do not place Figure 9 shows a generalized PCB layout guide for these components too close to the PH trace. Due to the TPS54372. the size of the IC package and the device pinout, they have to be routed somewhat close, but maintain The VIN pins should be connected together on the as much separation as possible while still keeping the printed-circuit board (PCB) and bypassed with a layout compact. low-ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass Connect the bias capacitor from the VBIAS pin to capacitor connections, the VIN pins, and the analog ground using the isolated analog ground TPS54372 ground pins. The minimum recommended trace. If an RT resistor is used, connect it to this trace bypass capacitance is 10-µF ceramic with a X5R- or as well. X7R-grade dielectric, and the optimum placement is closest to the VIN pins and the PGND pins. PERFORMANCE The TPS54372 has two internal grounds (analog and power). Inside the TPS54372, the analog ground ties For operation at full rated load current, the analog to all of the noise-sensitive signals, while the power ground plane must provide adequate heat dissipating ground ties to the noisier power signals. Noise area. A 3-inch by 3-inch plane of 1-ounce copper is injected between the two grounds can degrade the recommended, though not mandatory, depending on performance of the TPS54372, particularly at higher ambient temperature and airflow. Most applications output currents. Ground noise on an analog ground have larger areas of internal ground plane available, plane can also cause problems with some of the and the PowerPAD should be connected to the control and bias signals. For these reasons, separate largest area available. Additional areas on the top or analog and power ground traces are recommended. bottom layers also help dissipate heat, and any area There should be an area of ground on the top layer available should be used when 3-A or greater oper- directly under the IC, with an exposed area for ation is desired. Connection from the exposed area of connection to the PowerPAD. Use vias to connect the PowerPAD to the analog ground plane layer this ground area to any internal ground planes. Use should be made using 0.013-inch diameter vias to additional vias at the ground side of the input and avoid solder wicking through the vias. Six vias should output filter capacitors as well. The AGND and PGND be in the PowerPAD area with four additional vias pins should be tied to the PCB ground by connecting located under the device package. The size of the them to the ground area under the device as shown. vias under the package, but not in the exposed The only components that should tie directly to the thermal pad area, can be increased to 0.018 inch. power ground plane are the input capacitors, the Additional vias beyond the ten recommended that output capacitors, the input voltage decoupling ca- enhance thermal performance should be included in pacitor, and the PGND pins of the TPS54372. Use a areas not under the device package. 9 |
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