Error

Amplifier

R

Q

S

Boot

Charge

Boot

UVLO

Current

Sense

Oscillator

Frequency

Shift

Gate

Drive

Logic

Slope

Compensation

PWM

Latch

PWM

Comparator

ECO-MODE

Minimum Clamp

™

Maximum

Clamp

Voltage

Reference

Discharge

Logic

VSENSE

COMP

PH

BOOT

VIN

GND

Thermal

Shutdown

EN

Enable

Comparator

Shutdown

Logic

Shutdown

Enable

Threshold

S

1.25 V

0.8 V

80 mW

165 C

2.1V

12 A/V

SS

Shutdown

VSENSE

1 A

m

3 A

m

gm = 92 A/V

DC gain = 800 V/V

BW = 2.7 MHz

m

2 kW

2 A

m

TPS54331D

TPS54331

SLVS839F – JULY 2008 – REVISED OCTOBER 2014

www.ti.com

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Fixed-Frequency PWM Control

The TPS54331 device uses a fixed-frequency, peak-current mode control. The internal switching frequency of

the TPS54331 device is fixed at 570 kHz.

The voltage reference system produces a ±2% initial accuracy voltage reference (±3.5% over temperature) by

scaling the output of a temperature-stable bandgap circuit. The typical voltage reference is designed at 0.8 V.

8.3.3 Bootstrap Voltage (BOOT)

The TPS54331 device has an integrated boot regulator and requires a 0.1-

μF ceramic capacitor between the

BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. A ceramic capacitor with an

X7R- or X5R-grade dielectric is recommended because of the stable characteristics over temperature and

voltage. To improve drop out, the TPS54331 device is designed to operate at 100% duty cycle as long as the

BOOT-to-PH pin voltage is greater than 2.1 V (typical).

8.3.4 Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)

The EN pin has an internal pullup current-source that provides the default condition of the device while operating

when the EN pin floats.

10

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