CY27EE16ZE
Document #: 38-07440 Rev. *B
Page 3 of 17
Output Enable (OE) – Active HIGH
The default clock configuration has pin 10 programmed as an
Output Enable (OE). This pin enables the divider bank clock
outputs when HIGH, and disables divider bank clock outputs
when LOW.
Power-down Mode (PDM) – Active LOW
The Power-down Mode (PDM) function is available when pin
10 of the CY27EE16ZE is configured as PDM. When the PDM
signal pulled LOW, all clock components are shut down and
the part enters a low-power state. To configure pin 10 of the
CY27EE16ZE as PDM, see "Power-down Mode (PDM) and
Output Enable (OE) Registers for Pin 10", page 7.
Serial Programming Interface (SPI)
The SPI uses industry-standard signaling in both standard and
fast modes to program the 8 x 2 kbit EPPROM blocks of
scratchpad, the 2-kbit EEPROM dedicated to clock configu-
ration, and the 2-kbit SRAM block. See sections beginning
with "Using the Serial Programming Interface (SPI)", page 3
for more information.
Default Start-up Condition for CY27EE16ZE
The default (programmed) condition of the 8 x 256 bit
EEPROM blocks (scratchpad) in the device as shipped from
the factory, are blank and unprogrammed. In this condition, all
bits are set to 0.
The default clock configuration is:
•the crystal oscillator circuit is active.
•CLOCK1 outputs REF frequency.
•All other outputs are three-stated.
•WP control on pin 17.
•OE control on pin 10.
This default clock configuration is typically customized to meet
the needs of a specific application. It provides a clock signal
upon power-on, to facilitate in-system programming. Alterna-
tively, the CY27EE16ZE may be programmed with a different
clock configuration prior to placement of the CY27EE16ZE in
systems. While you can develop your own subroutine to
program any or all of the individual registers described in the
following pages, it may be easier to use CyClocksRT™ to
produce the required register setting file.
Using the Serial Programming Interface (SPI)
The CY27EE16ZE provides an industry-standard serial
programming interface for volatile and nonvolatile, in-system
programming of unique frequencies and options. Serial
programming and reprogramming allows for quick design
changes and product enhancements, eliminates inventory of
old design parts, and simplifies manufacturing.
The CY27EE16ZE is a group of ten slave devices with
addresses as shown in Figure 1. The serial programming
interface address of the CY27EE16ZE clock configuration
2-kbit EEPROM block is 69H. The serial programming
interface address of the CY27EE16ZE clock configuration
2-kbit SRAM block is 68H. Should there be a conflict with any
other devices in your system, all device addresses can also be
changed using CyberClocks. Registers in the clock configu-
ration 2-kbit SRAM memory block are written, when the user
wants to update the clock configuration for on-the-fly changes
.
Registers in the clock configuration EEPROM block are
written, if the user wants to update the clock configuration so
that it is saved and used again after power-up or reset.
All
programmable
registers
in
the
CY27EE16ZE
are
addressed with eight bits and contain eight bits of data. Table 2
lists the specific register definitions and their allowable values.
See section "Serial Programming Interface Timing", page 12,
for a detailed description.
1st
EE block
256 x 8 bits
Address:
1000000
4th
EE block
256 x 8 bits
Address:
1000011
3rd
EE block
256 x 8 bits
Address:
1000010
2nd
EE block
256 x 8 bits
Address:
1000001
clock config.
EE block
256 x 8 bits
Address:
1101000
clock config.
SRAM
256 x 8 bits
Address:
1101001
5th
EE block
256 x 8 bits
Address:
1000100
8th
EE block
256 x 8 bits
Address:
1000111
7th
EE block
256 x 8 bits
Address:
1000110
6th
EE block
256 x 8 bits
Address:
1000101
Figure 1. Device Addresses for EEPROM Scratchpad and Clock Configuration Blocks
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