64K/128K x 8/9 Dual-Port Static RAM
CY7C008/009
CY7C018/019
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06041 Rev. *C
Revised June 22, 2004
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 64K x 8 organization (CY7C008)
• 128K x 8 organization (CY7C009)
• 64K x 9 organization (CY7C018)
• 128K x 9 organization (CY7C019)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12[1]/15/20 ns
• Low operating power
— Active: ICC = 180 mA (typical)
— Standby: ISB3 = 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
Notes:
1.
See page 6 for Load Conditions.
2.
I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
3.
A0–A15 for 64K devices; A0–A16 for 128K.
4.
BUSY is an output in master mode and an input in slave mode.
I/O
Control
Address
Decode
A0L–A15/16L
CEL
OEL
R/WL
BUSYL
I/O
Control
Interrupt
Semaphore
Arbitration
SEML
INTL
M/S
Logic Block Diagram
A0L–A15/16L
True Dual-Ported
RAM Array
A0R–A15/16R
CER
OER
R/WR
BUSYR
SEMR
INTR
Address
Decode
A0R–A15/16R
[2]
[2]
[3]
[3]
[4]
[4]
[3]
[3]
R/WL
CE0L
CE1L
OEL
I/O0L–I/O7/8L
CEL
R/WR
CE0R
CE1R
OER
I/O0R–I/O7/8R
CER
16/17
8/9
16/17
8/9
16/17
16/17
CY7C008/009
CY7C018/01964K/128K x 8/9 Dual-Port Static RAM