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5962-9675801QXA Datasheet(PDF) 11 Page - Texas Instruments |
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5962-9675801QXA Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 97 page  1–6 1.5 Terminal Functions (Continued)† TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION HSYNCOUT, VSYNCOUT 69, 70 O Horizontal and vertical sync outputs. These outputs are pipeline delayed versions of the selected sync inputs. Output polarity inversion may be independently selected using general control register bits GCR(1,0). IOR, IOG, IOB 72, 74, 76 O Analog current outputs. These outputs can drive a 37.5- Ω load directly (doubly terminated 75- Ω line), thus eliminating the requirement for any external buffering. GI/O4 – GI/O0 59 – 61, 63, 64 I/O Software programmable general I/O terminals that can be used to control external devices. LCLK 126 I Latch clock input. LCLK is used to latch pixel-bus-input data and system video controls. VGA data may also be latched with LCLK if so selected. LCLK may be a delayed version of RCLK provided that linear phase changes in RCLK cause corresponding linear phase changes in LCLK. MCLK 124 O Memory clock output. MCLK is the output of an independently programmable PLL frequency synthesizer. The frequency range is 14 – 100 MHz. The dot clock may be output on this terminal while the MCLK frequency is reprogrammed. See Section 2.4.2.1. PCLKOUT 148 O Pixel clock PLL output. PCLKOUT is a buffered version of the pixel clock PLL output and is mainly for test purposes. This output is independent of the dot clock source selected by the clock selection register. PLLGND 146 Ground for PLL supplies. Decoupling capacitors should be connected between PLLVDD and PLLGND. PLLGND should be connected to the system ground through a ferrite bead. PLLVDD 147, 150 PLL power supply. PLLVDD must be a well regulated 5 V power supply voltage. Decoupling capacitors should be connected between PLLVDD and PLLGND. Terminal 143 supplies power to the pixel clock PLL. Terminal 146 supplies power to the MCLK PLL and the loop clock PLL. OVS 98 I Overscan input. OVS is used to control the display of custom screen borders. If OVS is not used, it should be connected to GND. ODD/EVEN 125 I Odd or even field display. ODD/EVEN indicates odd or even field during interlaced display for cursor operation. Logic 0 indicates the even field and logic 1 indicates the odd field. See Section 2.7.4 for cursor operation in interlace mode. PLLSEL0, PLLSEL1 1, 164 I Pixel clock PLL frequency selection. Selects among two fixed frequencies and the programmed frequency of the pixel clock PLL. PSEL 99 I Port select. PSEL provides the capability of switching between direct color and true color or overlay. Multiple true color or overlay windows may be displayed using the PSEL control. Since PSEL is sampled with LCLK, the granularity for switching dependes on the number of pixels loaded per LCLK. If PSEL is not used, it should be connected to GND. P33–P16 P19–P18 P22–P0 P63–P57 P56–P48 P47–P44 P43–P34 3 – 16, 19, 20, 22 – 39, 113 – 119, 130 – 138, 141 – 145, 153 – 162 I Pixel input port. The port can be used in various modes as described in Section 2.6. Unused terminals should not be allowed to float. † All unused inputs should be tied to a logic level and not be allowed to float. |
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