SWITCHING FREQUENCY

100 k

R

500 kHz

=

×

TPS54310

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SLVS412E – DECEMBER 2001 – REVISED DECEMBER 2014

Feature Description (continued)

(3)

External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 700 kHz by driving

a synchronization signal into SYNC and connecting a resistor from RT to AGND. Choose an RT resistor that sets

the free-running frequency to 80% of the synchronization signal. Table 1 summarizes the frequency selection

configurations.

Table 1. Summary of the Frequency Selection Configurations

SWITCHING FREQUENCY

SYNC PIN

RT PIN

350 kHz, internally set

Float or AGND

Float

550 kHz, internally set

≥ 2.5 V

Float

Externally set 280 kHz to 700 kHz

Float

R = 68 k to 180 k

Externally synchronized frequency

Synchronization signal

R = RT value for 80% of external synchronization frequency

8.3.6 Error Amplifier

The high performance, wide bandwidth, voltage error amplifier sets the TPS54310 apart from most dc/dc

converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the

particular needs of the application. Type 2 or type 3 compensation can be employed using external

compensation components.

8.3.7 PWM Control

Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic.

Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch,

and portions of the adaptive dead-time and control logic block. During steady-state operation below the current

limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch.

Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse

duration. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to

charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the

error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and

turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM

ramp.

During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the

PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on

until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The

device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting

continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE

voltage decreases to a range that allows the PWM comparator to change states. The TPS54310 is capable of

sinking current continuously until the output reaches the regulation set-point.

If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds

the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the

output inductor and consequently the output current. This process is repeated each cycle in which the current

limit comparator is tripped.

8.3.8 Dead-Time Control and MOSFET Drivers

Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs

during the switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side

driver does not turn on until the gate drive voltage to the low-side FET is below 2 V. The low-side driver does not

turn on until the voltage at the gate of the high-side MOSFETs is below 2 V. The high-side and low-side drivers

are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side

driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an

external BOOT capacitor and an internal 2.5-

Ω bootstrap switch connected between the VIN and BOOT pins.

The integrated bootstrap switch improves drive efficiency and reduces external component count.

Copyright © 2001–2014, Texas Instruments Incorporated

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