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CS8406-DZ Datasheet(PDF) 4 Page - Cirrus Logic |
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CS8406-DZ Datasheet(HTML) 4 Page - Cirrus Logic |
4 / 43 page CS8406 4 DS580F1 LIST OF FIGURES Figure 1. Audio Port Master Mode Timing....................................................................................... 8 Figure 2. Audio Port Slave Mode and Data Input Timing ................................................................ 8 Figure 3. SPI Mode timing ............................................................................................................... 9 Figure 4. I²C Mode timing .............................................................................................................. 10 Figure 5. Recommended Connection Diagram for Software Mode............................................... 11 Figure 6. Recommended Connection Diagram for Hardware Mode ............................................. 12 Figure 7. Serial Audio Input Example Formats.............................................................................. 15 Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data .............................................. 18 Figure 9. Control Port Timing in SPI Mode.................................................................................... 19 Figure 10. Control Port Timing, I²C Slave Mode Write .................................................................. 20 Figure 11. Control Port Timing, I²C Slave Mode Read .................................................................. 20 Figure 12. Hardware Mode Data Flow .......................................................................................... 32 Figure 13. Professional Output Circuit ..........................................................................................39 Figure 14. Consumer Output Circuit (VL = 5.0 V) ......................................................................... 39 Figure 15. TTL/CMOS Output Circuit ............................................................................................ 39 Figure 16. Channel Status Data Buffer Structure .......................................................................... 40 Figure 17. Flowchart for Writing the E Buffer ................................................................................ 41 LIST OF TABLES Table 1. Control Register Map Summary ...................................................................................... 22 Table 2. Hardware Mode COPY/C and ORIG pin functions.......................................................... 33 Table 3. Hardware Mode Serial Audio Port Format Selection....................................................... 33 Table 4. Hardware Mode OMCK Clock Ratio Selection ................................................................ 33 Table 5. Equivalent Register Settings of Serial Audio Input Formats Available in Hardware Mode ............................................................................... 33 Table 6. Revision History .............................................................................................................. 43 |
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