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C9531
Document #: 38-07034 Rev. *D
Page 4 of 10
2
0
Not used
1
0
Not used
0
1
HWSEL
Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, and 15), 0 = SMBus
Byte 0 bits 3, 4, & 6
Table 4. Clarification Table for Byte0, bit 5
Byte0, bit6
Byte0, bit5
Description
0
0
Frequency generated from second PLL
0
1
Frequency generated from XIN
1
0
Spread @ –1.0%
1
1
Spread @ –0.5%
Table 5. Test Table
Test Function Clock
Outputs
Note
CLK
REF
Frequency
XIN/4
XIN
XIN is the frequency of the clock that is present on the
XIN input during test mode.
Byte 1: CPU Register
Bit
@Pup
Name
Description
71
Reserved
61
Reserved
5
1
REFEN
REF Output Enable
0 = Disable, 1= Enable
41
Reserved
31
Reserved
21
Reserved
11
Reserved
01
Reserved
Byte 2: PCI Register
Bit
@Pup
Name
Description
71
Reserved
61
Reserved
51
Reserved
4
1
18
CLK4 Output Enable
0 = Disable, 1= Enable
3
1
19
CLK3 Output Enable
0 = Disable, 1= Enable
2
1
22
CLK2Output Enable
0 = Disable, 1= Enable
1
1
23
CLK1 Output Enable
0 = Disable, 1= Enable
0
1
24
CLK0 Output Enable
0 = Disable, 1= Enable
Byte 0: Output Register (continued)
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