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TPS53632RSMT Datasheet(PDF) 8 Page - Texas Instruments |
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TPS53632RSMT Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 43 page  TPS53632 SLUSBW8 – SEPTEMBER 2014 www.ti.com 6.6 Timing Requirements The TPS53632 requires the ENABLE signal on Pin 8 to go from low to high only after the V5A (5V), the VDD (3.3V) and the VIN rails have gone high. 6.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Controller minimum OFF tOFF(min) Fixed value 20 time ns Controller minimum ON tON(min) RCF = 150 kΩ, VVIN = 20 V, VVFB = 0 V 20 time TIMERS: SLEW RATE, ADDR, SLEEP EXIT, ON TIME AND I/O TIMING tSTART-CB Cold boot time(1) VBOOT > 0V , EN = high, CREF = 0.33 µF 1.2 ms tSTBY-E Standby exit time(2) VVID = 1.28 V, RSLEW = 39 kΩ 250 µs RSLEW = 20 kΩ 6 RSLEW = 24 kΩ 12 Slew rate setting for VID SLSET RSLEW = 30 kΩ 18 mV/µs change RSLEW = 39 kΩ 24 RSLEW = 56 kΩ 30 Slew rate setting for start- SLSTART (3) EN goes high, RSLEW = 39 kΩ 12 mV/µs up VSLEWA ≤ 0.30 V (Addr = 100 0xxx) 000b Address setting 3 LSB of ADDR 0.75 V ≤ VSLEWA ≤ 0.85 V 011b I2C address 1.15 V ≤ VSLEWA ≤ 1.25 V 101b PGOOD deglitch time tPGDDGLTO 1 (over)(4) µs PGOOD deglitch time tPGDDGLTU 31 (under)(5) RCF = 20 kΩ 295 RCF = 24 kΩ, VVIN = 12 V, VVFB = 1 V (400 kHz) 230 tON On time RCF = 39 kΩ, VVIN = 12 V, VVFB = 1 V (600 kHz) 164 ns RCF = 75 kΩ, VVIN = 12 V, VVFB = 1 V (800 kHz) 140 RCF = 150 kΩ, VVIN = 12 V, VVFB = 1 V (1 MHz) 128 PWM AND SKIP OUTPUTS PWMx/SKIP H-L transition tP-S_H-L (3) 10% to 90%, both edges 7 20 time ns tP-S_TRI (3) PWMx tri-state transition 10% or 90% to tri-state level, both edges 5 20 PROTECTION: OVP, UVP, PGOOD AND THERMAL SHUTDOWN PGOOD low after enable tPG2 Low state time after EN goes low. 225 250 275 µs goes low (1) Cold boot time is defined as the time from UVLO detection to VOUT ramp. (2) Standby exit time is defined as the time from EN assertion until PGOOD goes high (3) Specified by design. Not production tested. (4) PGOOD deglitch time (over) is defined as the time from when the VFB pin rises above the 250-mV VDAC boundary to when the PGOOD pin goes low. (5) PGOOD deglitch time (under) is defined as the time from when the VFB pin falls below the –300-mV VDAC boundary to when the PGOOD pin goes low. 8 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: TPS53632 |
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