DS90C032B datasheet(5/9 Pages) NSC

Part #	DS90C032B

Description	LVDS Quad CMOS Differential Line Receiver

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Manufacturer	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

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Typical Application

Applications Information

LVDS drivers and receivers are intended to be primarily used

in an uncomplicated point-to-point configuration as is shown

in

Figure 5. This configuration provides a clean signaling en-

vironment for the quick edge rates of the drivers. The re-

ceiver is connected to the driver through a balanced media

which may be a standard twisted pair cable, a parallel pair

cable, or simply PCB traces. Typically the characteristic im-

pedance of the media is in the range of 100

Ω. A termination

resistor of 100

Ω should be selected to match the media, and

is located as close to the receiver input pins as possible. The

termination resistor converts the current sourced by the

driver into a voltage that is detected by the receiver. Other

configurations are possible such as a multi-receiver configu-

ration, but the effects of a mid-stream connector(s), cable

stub(s), and other impedance discontinuities as well as

ground shifting, noise margin limits, and total termination

loading must be taken into account.

The DS90C032B differential line receiver is capable of de-

tecting signals as low as 100 mV, over a ±1V common-mode

range centered around +1.2V. This is related to the driver off-

set voltage which is typically +1.2V. The driven signal is cen-

tered around this voltage and may shift ±1V around this cen-

ter point. The ±1V shifting may be the result of a ground

potential difference between the driver’s ground reference

and the receiver’s ground reference, the common-mode ef-

fects of coupled noise, or a combination of the two. Both re-

ceiver input pins should honor their specified operating input

voltage range of 0V to +2.4V (measured from each pin to

ground), exceeding these limits may turn on the ESD protec-

tion circuitry which will clamp the bus voltages.

Receiver Fail-Safe:

The LVDS receiver is a high gain, high speed device that

amplifies a small differential signal (20mV) to CMOS logic

levels. Due to the high gain and tight threshold of the re-

ceiver, care should be taken to prevent noise from appearing

as a valid signal.

The receiver’s internal fail-safe circuitry is designed to

source/sink a small amount of current, providing fail-safe

protection (a stable known state of HIGH output voltage) for

floating or terminated receiver inputs.

1.

Open Input Pins. The DS90C032B is a quad receiver

device, and if an application requires only 1, 2 or 3 re-

ceivers, the unused channel(s) inputs should be left

OPEN. Do not tie unused receiver inputs to ground or

any other voltages. The input is biased by internal high

value pull up and pull down resistors to set the output to

a HIGH state. This internal circuitry will guarantee a

HIGH, stable output state for open inputs.

2.

Terminated Input. If the driver is disconnected (cable

unplugged), or if the driver is in a TRI-STATE or

power-off condition, the receiver output will again be in a

HIGH state, even with the end of cable 100

Ω termination

resistor across the input pins. The unplugged cable can

become a floating antenna which can pick up noise. If

the cable picks up more than 10mV of differential noise,

the receiver may see the noise as a valid signal and

switch.

To

insure

that

any

noise

is

seen

as

common-mode and not differential, a balanced intercon-

nect should be used. Twisted pair cable will offer better

balance than flat ribbon cable.

The footprint of the DS90C032B is the same as the industry

standard 26LS32 Quad Differential (RS-422) Receiver.

For additional LVDS application information, please refer to

National’s LVDS Owner’s Manual available through Nation-

al’s website www.national.com/appinfo/lvds.

DS100990-7

FIGURE 5. Point-to-Point Application

www.national.com

5

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DS90C032B Datasheet(PDF) 5 Page - National Semiconductor (TI)

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