TLV5610IYE

TLV5608IYE

SLAS393 − OCTOBER 2003

www.ti.com

2

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS

PACKAGE

TA

WCS(1)

(YE)

−40

°C to 85°C

TLV5610IYE

−40

°C to 85°C

TLV5608IYE

(1) Wafer chip scale package. See Figure 13.

FUNCTIONAL BLOCK DIAGRAM

OUTA

12/10

12/10

Serial

Interface

12

8

REF

SCLK

DIN

FS

MODE

DOUT

DAC B, C, D, E, F, G and H

Same as DAC A

OUT

PRE

LDAC

X2

B, C, D,

E, F, G

and H

DAC A

Holding

Latch

DAC A

Latch

12/10

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AGND

10

P

Analog ground

AVDD

11

P

Analog power supply

DGND

1

P

Digital ground

DIN

2

I

Digital serial data input

DOUT

19

O

Digital serial data output

DVDD

20

P

Digital power supply

FS

4

I

Frame sync input

LDAC

18

I

Load DAC. The DAC outputs are only updated, if this signal is low. It is an asynchronous input.

MODE

17

I

DSP/

µC mode pin. High = µC mode, NC = DSP mode.

PRE

5

I

Preset input

REF

16

I

Voltage reference input

SCLK

3

I

Serial clock input

OUTA−OUTH

12−15,

6−9

O

DAC outputs A, B, C, D, E, F, G and H