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TPS40211DGQG4 Datasheet(PDF) 11 Page - Texas Instruments |
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TPS40211DGQG4 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 44 page  2 5 4 SS COMP FB TPS40210/11 R SS(chg) UDG-07121 + + R SS(dchg) 700 mV REF OC Fault UVLO DIS Error Amplifier V SSE(1) V SS V OUT V SSE V SS(ofst) t 0 t 1 V SS(ofst)+700 mV V IN - VD t 2 t 3 11 TPS40210, TPS40211 www.ti.com SLUS772F – MARCH 2008 – REVISED MARCH 2015 Product Folder Links: TPS40210 TPS40211 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Soft-Start The soft-start feature of the TPS40210/11 is a closed-loop soft-start, meaning that the output voltage follows a linear ramp that is proportional to the ramp generated at the SS pin. This ramp is generated by an internal resistor connected from the BP pin to the SS pin and an external capacitor connected from the SS pin to GND. The SS pin voltage (VSS) is level shifted down by approximately VSS(ofst) (approximately 700 mV) and sent to one of the “+” (the “+” input with the lowest voltage dominates) inputs of the error amplifier. When this level shifted voltage (VSSE) starts to rise at time t1 (see Figure 20), the output voltage the controller expects, rises as well. Since VSSE starts at near 0 V, the controller attempts to regulate the output voltage from a starting point of zero volts. It cannot do this due to the converter architecture. The output voltage starts from the input voltage less the drop across the diode (VIN - VD) and rises from there. The point at which the output voltage starts to rise (t2) is the point where the VSSE ramp passes the point where it is commanding more output voltage than (VIN - VD). This voltage level is labeled VSSE(1). The time required for the output voltage to ramp from a theoretical zero to the final regulated value (from t1 to t3) is determined by the time it takes for the capacitor connected to the SS pin (CSS) to rise through a 700-mV range, beginning at VSS(ofst) above GND. Figure 20. SS Pin Voltage and Output Voltage Figure 21. SS Pin Functional Circuit |
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