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TPS40055PWPRG4 Datasheet(PDF) 9 Page - Texas Instruments |
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TPS40055PWPRG4 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 39 page ( ) ( ) KFF IN(min) KFF T R V V 58.14 R 1340 = - ´ ´ + W VPEAK VVALLEY tON1 > tON2 and D1 > D2 t2 tON2 t1 tON1 VIN RAMP COMP SW D = tON t UDG-08119 TPS40054, TPS40055, TPS40057 www.ti.com SLUS593I – DECEMBER 2003 – REVISED DECEMBER 2014 Feature Description (continued) Figure 6. Voltage Feed-Forward Effect On Pwm Duty Cycle The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The PWM ramp time is programmed via a single resistor (RKFF) pulled up to VIN. RKFF is related to RT, and the minimum input voltage, VIN(min) through the following: where • VIN(min) is the ensured minimum startup voltage (the actual startup voltage is nominally about 10% lower at 25°C). VIN(min) should be programmed equal to or greater than 8.0 V to ensure start-up and shutdown through the programmed UVLO through KFF pin. • RT is the timing resistance in kΩ • VKFF is the voltage at the KFF pin (typical value is 3.48 V) (2) The curve showing the RKFF required for a given switching frequency, fSW, and VUVLO is shown in Figure 2. For low-input voltage and high duty-cycle applications, the voltage feed-forward may limit the duty cycle prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and regulates the output voltage. For more information on large duty cycle operation, refer to Application Note (SLUA310), Effect of Programmable UVLO on Maximum Duty Cycle. 7.3.3 UVLO Operation The TPS4005x uses variable (user-programmable) UVLO protection. See the Programming the Ramp Generator section for more information on setting the UVLO voltage. The UVLO circuit holds the soft-start low until the input voltage exceeds the user-programmable undervoltage threshold. The TPS4005x uses the feed-forward pin, KFF, as a user-programmable low-line UVLO detection. This variable low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An undervoltage condition exists if the TPS4005x receives a clock pulse before the ramp has reached 90% of its full amplitude. The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF pin. The KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF resistor can be referenced to the oscillator frequency as descibed in Equation 2. The programmable UVLO function uses a 3-bit counter to prevent spurious shut-downs or turn-ons due to spikes or fast line transients. When the counter reaches a total of seven counts in which the ramp duration is shorter than the clock cycle, a powergood signal is asserted and a soft-start initiated, and the upper and lower MOSFETS are turned off. Once the soft-start is initiated, the UVLO circuit must see a total count of seven cycles in which the ramp duration is longer than the clock cycle before an undervoltage condition is declared (see Figure 7). Copyright © 2003–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS40054 TPS40055 TPS40057 TPS40054: Not Recommended For New Designs |
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