TPS40056

SLVS612 − APRIL 2006

7

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APPLICATION INFORMATION

The TPS40056 allows the user to optimize the PWM controller to the specific application.

The TPS40056 is the controller of choice for synchronous buck designs, the output of which is required to track

another voltage. It has two quadrant operation and can source or sink output current, providing the best transient

response.

SW NODE RESISTOR AND DIODE

The SW node of the converter will be negative during the dead time when both the upper and lower MOSFETs

are off. The magnitude of this negative voltage is dependent on the lower MOSFET body diode and the output

current which flows during this dead time. This negative voltage could affect the operation of the controller,

especially at low input voltages.

Therefore, a resistor ( 3.3

Ω to 4.7 Ω) and Schottky diode must be placed between the lower MOSFET drain

and pin 12, SW, of the controller as shown in Figure 10. The Schottky diode must have a voltage rating to

accommodate the input voltage and ringing on the SW node of the converter. A 30-V Schottky such as a BAT54

or a 40-V Schottky such as a Zetex ZHCS400 or Vishay SD103AWS are adequate. These components are

SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)

The TPS40056 has independent clock oscillator and ramp generator circuits. The clock oscillator serves as the

R

1

f

SW

17.82

* 23 kW

UVLO OPERATION

The TPS40056 uses fixed UVLO protection. The fixed UVLO monitors the input voltage. The UVLO circuit holds

the soft-start low until the input voltage has exceeded the undervoltage threshold.

divider(s) R4,R5,R1 and R6 as shown in Figure 1. The voltage on the EA_REF input should be in the range of

0.2 V to 2.5 V. If the output voltage is less than 2.5 V, resistor R6 can be omitted. For example in the DDR case,

in Equation (2).

V

R5

R4

) R5

R6

) R1

R6

V

(1)

(2)