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OPA650NB-3K Datasheet(PDF) 7 Page - Texas Instruments

Part # OPA650NB-3K
Description  Wideband, Low Power Voltage Feedback OPERATIONAL AMPLIFIER
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

OPA650NB-3K Datasheet(HTML) 7 Page - Texas Instruments

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®
OPA650
7
the ground and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power and
ground traces to minimize inductance between the pins and
the decoupling capacitors. Larger (2.2
µF to 6.8µF) decoupling
capacitors, effective at lower frequencies, should also be
used. These may be placed somewhat farther from the
device and may be shared among several devices in the same
area of the PC board.
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of the
OPA650. Resistors should be a very low reactance type.
Surface mount resistors work best and allow a tighter overall
layout. Metal film or carbon composition axially-leaded
resistors can also provide good high frequency performance.
Again, keep their leads as short as possible. Never use
wirewound type resistors in a high frequency application.
Since the output pin and the inverting input pin are most
sensitive to parasitic capacitance, always position the feed-
back and series output resistor, if any, as close as possible to
the package pins. Other network components, such as non-
inverting input termination resistors, should also be placed
close to the package.
Even with a low parasitic capacitance shunting external
resistors, excessively high resistor values can create signifi-
cant time constants and degrade performance. Good metal
film or surface mount resistors have approximately 0.2pF in
shunt with the resistor. For resistor values > 1.5k
Ω, this adds
a pole and/or zero below 500MHz that can affect circuit
operation. Keep resistor values as low as possible consistent
with output loading considerations. The 402
Ω feedback
used for the Typical Performance Plots is a good starting
point for design. Note that a 25
Ω feedback resistor, rather
than a direct short, is suggested for a unity gain follower.
This effectively reduces the Q of what would otherwise be
a parasitic inductance (the feedback wire) into the parasitic
capacitance at the inverting input.
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for Gain of +1.
HARMONIC DISTORTION vs GAIN
(f
O = 5MHz, VO = 2Vp-p)
–40
–50
–60
–70
–80
1
2
3
4
5
6
789
10
Non-Inverting Gain (V/V)
3f
O
2f
O
DISCUSSION OF
PERFORMANCE
The OPA650 is a low power, wideband voltage feedback
operational amplifier. Each channel is internally compen-
sated to provide unity gain stability. The OPA650’s voltage
feedback architecture features true differential and fully sym-
metrical inputs. This minimizes offset errors, making the
OPA650 well suited for implementing filter and instrumen-
tation designs. The OPA650’s AC performance is optimized
to provide a gain bandwidth product of 180MHz and a fast
0.1% settling time of 10.2ns, which is an important consid-
eration in high speed data conversion applications. Along
with its excellent settling characteristics, the low DC input
offset of
±1mV and drift of ±3µV/°C support high accuracy
requirements. In applications requiring a higher slew rate and
wider bandwidth, such as video and high bit rate digital
communications, consider the current feedback OPA658.
CIRCUIT LAYOUT AND BASIC OPERATION
Achieving optimum performance with a high frequency am-
plifier like the OPA650 requires careful attention to layout
parasitics and selection of external components. Recommen-
dations for PC board layout and component selection include:
a) Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability; on the non-
inverting input it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance (< 0.25") from the two power pins
to high frequency 0.1
µF decoupling capacitors. At the pins,


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