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DETAILED DESCRIPTION

EQUALIZER

LIMITER

OUTPUT SIGNAL WAVEFORM SHAPING

HIGH-SPEED OUTPUT DRIVER

MODULATION CURRENT GENERATOR

DC OFFSET CANCELLATION AND CROSS POINT CONTROL

ONET8501V

SLLS837B – JUNE 2007 – REVISED SEPTEMBER 2007

The data signal can be applied to an input equalizer by means of the input signal pins DIN+/DIN–, which provide

on-chip differential 100

Ω line-termination. The equalizer is enabled by setting the EQENA = 1 (bit 1 of register 0).

Equalization of up to 300mm (12”) of microstrip or stripline transmission line on FR4 printed circuit boards can be

achieved. The amount of equalization is digitally controlled by the two-wire interface and control logic block and

depends on the register settings EQADJ[0..7] (register 3). The equalizer can also be turned off and bypassed by

setting EQENA = 0. For details about the equalizer settings, see Table 16.

By limiting the output signal of the equalizer to a fixed value, the limiter removes any overshoot after the input

equalization and provides the input signal for the output signal waveform shaping.

The output signal waveform shaping provides two paths for the data signal. The delay buffer ensures that both

paths have the same transit time. The over- and undershoot peaking width and height are controlled through the

two wire interface and the peak driver linearly amplifies the signal. The resultant waveform shaped signal is then

added to the output of the main driver. The overshoot width is controlled by register 5 settings OSW[0..3] and the

overshoot height is controlled by register 6 settings OSH[0..3]. The undershoot width is controlled by register 7

settings USW[0..3] and the undershoot height is controlled by register 8 settings OSH[0..3].

The peaking current is disabled by setting both over- and undershoot height registers to zero. The peaking

current is also disabled when the DIS pin is set to a high level or during a fault condition if the fault detection

enable register flag FLTEN is set (bit 3 of register 0).

The modulation current is sunk from the common emitter node of the output driver differential pair by means of a

modulation current generator, which is digitally controlled by the 2-wire serial interface.

The collector nodes of the output stages are connected to the output pins MOD+/ MOD–, which include on-chip 2

× 50Ω back-termination to VCC. The 50Ω back-termination together with an optional off chip series resistor helps

to sufficiently suppress signal distortion caused by double reflections for VCSEL diodes with impedances from

50

Ω through 110Ω. The polarity of the output can be selected with the output polarity switch POL (bit 4 of

register 9).

The modulation current generator provides the current for the current modulator described above. The circuit is

digitally controlled by the 2-wire interface block.

An 8-bit wide control bus, MODC[0..7] (register 1), is used to set the desired modulation current. Furthermore,

four modulation current ranges can be selected by means of MODRNG1 (bit 1 of register 13) and MODRNG0 (bit

0 of register 13).

The modulation current can be disabled by setting the DIS input pin to a high level. The modulation current is

also disabled in a fault condition if the fault detection enable register flag FLTEN is set (bit 3 of register 0).

The ONET8501V has DC offset cancellation to compensate for internal offset voltages. The offset cancellation

can be disabled by setting OCDIS = 1 (bit 2 of register 9). Disabling the offset cancellation enables the output

crossing point to be adjusted from 35% to 65% of the output eye diagram. The crossing point can be moved

toward the one level be setting CPSGN = 1 (bit 7 of register 4) and it can be moved toward the zero level by

setting CPSGN = 0. The percentage of shift depends upon the register settings CPADJ[0..6] (register 4).

Copyright © 2007, Texas Instruments Incorporated

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