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ONET1130EPRSMT Datasheet(PDF) 4 Page - Texas Instruments |
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ONET1130EPRSMT Datasheet(HTML) 4 Page - Texas Instruments |
4 / 55 page ONET1130EP SLLSEO4A – JUNE 2015 – REVISED JULY 2015 www.ti.com Pin Functions (continued) NUMBER NAME Type DESCRIPTION 2-wire interface serial data input. Requires an external 4.7-k Ω to10-kΩ pull-up resistor SDA 17 Digital-in/out to VCC. This pin is 3.3-V tolerant. 2-wire interface serial clock input. Requires an external 4.7-k Ω to10-kΩ pull-up SCK 18 Digital-in resistor to VCC. This pin is 3.3-V tolerant. Disables both bias and modulation currents when set to high state. Includes a 250-k Ω pull-up resistor to VCC. Requires an external 4.7 k Ω to 10 kΩ pull-up resistor to VCC TX_DIS 32 Digital-in for proper operation Toggle to reset a fault condition. This is an ORed function with the TXBIASEN bit (bit 2 in register 1). This pin is 3.3-V tolerant. Non-inverted transmitter data input. On-chip differentially 100 Ω terminated to TXIN–. TXIN+ 4 Analog-in Must be AC coupled. Inverted transmitter data input. On-chip differentially 100 Ω terminated to TXIN+. Must TXIN– 5 Analog-in be AC coupled. Transmitter fault detection flag. High level indicates that a fault has occurred. Open TX_FLT 31 Digital-out drain output. Requires an external 4.7 k Ω to 10 kΩ pull-up resistor to VCC for proper operation. This pin is 3.3-V tolerant. Inverted transmitter data output. Internally terminated in single-ended operation TXOUT– 12 CML-out mode. TXOUT+ 13 CML-out Non-Inverted transmitter data output. VCC_RX 27, 30 Supply 2.5 V ± 5% supply for the receiver. VCC_TX 11, 14 Supply 2.5 V ± 5% supply for the transmitter. VDD 15 Supply 2.5 V ± 5% supply for the digital circuitry. Exposed Pad EP Exposed die pad. Solder to the PCB. 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ONET1130EP |
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