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A4956 Datasheet(PDF) 7 Page - Allegro MicroSystems |
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A4956 Datasheet(HTML) 7 Page - Allegro MicroSystems |
7 / 11 page Full-Bridge PWM Gate Driver A4956 7 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com After the fast-decay time expires, the bridge will switch to slow decay for the remaining off-time. When the bridge is operating in fast decay, it will internally prevent current reversal by putting the bridge in a high-Z state if the current through the sense resis- tor falls close to zero. OCLn Output An open drain logic output will be driven low to indicate system operation. The OCLn terminal is driven low under two condi- tions: 1. When the system is limiting current to value set by VREF and RSENSE. Once overcurrent events are no longer detected, the A4956 will release the indication after a time tOCLn. 2. When a VDS fault is detected, the OCLn terminal is driven low. It is released when the fault is reset. The OCLn terminal, in combination with the AIOUT terminal, can provide valuable information about how the system is behav- ing: • Overcurrent events can indicate a motor stall condition, in which case the system controller can respond to the fault condition by reducing PWM duty. When OCLn is low and the voltage on AIOUT is greater than 0 V, the controller is actively limiting current with the internal, fixed off-time PWM current limiter. • In the case of a VDS fault, the OCLn terminal is also driven low, but the AIOUT voltage will be 0 V, because the bridge has been disabled. This notifies the user that a VDS fault has occurred and the driver has been disabled. AIOUT An analog output can be used to monitor current through the external sense resistor (if used). The SENSE voltage is gained by a factor of 10 and fed to the AIOUT terminal. A sample-and-hold circuit is used to capture the voltage across the sense resistor and holds it during periods when the voltage is not representative of the current in the motor. The AIOUT Output diagram illustrates when the voltage is held. The held voltage will droop at a rate equal to VDROOP. In the case of a VDS fault on the bridge, the AIOUT terminal will be discharged to zero volts. Charge Pump The Charge Pump is used to generate a supply above VBB to drive the high-side MOSFETs. The VCP voltage is internally monitored and, in the case of a fault condition, the outputs of the device are disabled. MOSFET VDS Protection The drain-to-source voltage is monitored across the MOSFET any time the MOSFET is on. If the voltage across the MOSFET exceeds VDSTHRES, the bridge is disabled and latched off. In order to prevent false VDS faults, the VDS monitor is blanked immediately after any MOSFET is turned on. The VDS monitor waits for a blank-time defined by the components on the RC ter- minal before monitoring the VDS level. During the off-time when SR is active, VDS blanking is fixed at 1 μs. VDS Fault When a VDS fault occurs, and the bridge is disabled, and the fault is latched, the OCLn terminal is immediately driven low. The latch can only be reset by going into standby or by dropping VBB below the UVLO threshold. Standby Mode Low power standby mode is activated when ENABLE is held logic LOW for TSTB (typically 1 ms). Standby mode disables most of the internal circuitry, including the charge pump and internal regulator. When coming out of standby mode, the A4956 requires up to 300 µs before the outputs can respond to input commands. TSD If the die temperature increases to approximately TTSD, the full bridge outputs will be disabled until the internal temperature falls below TTSD minus a hysteresis level of THYS. Fault Shutdown In the event of a fault due to excessive junction temperature, or low voltage on VCP or VBB, the outputs of the device are disabled until the fault condition is removed. At power-up, the UVLO circuit disables the drivers until the UVLO thresholds are exceeded. |
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