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A4933 Datasheet(PDF) 9 Page - Allegro MicroSystems |
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A4933 Datasheet(HTML) 9 Page - Allegro MicroSystems |
9 / 25 page Automotive 3-Phase MOSFET Driver A4933 9 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com In some applications a safety resistor is added between the gate and source of each FET in the bridge. When a high-side FET is held in the on-state, the current through the associated high-side gate-source resistor (RGSH) is provided by the high-side drive and therefore appears as a static resistive load on the top-off charge pump. The minimum value of RGSH for which the top-off charge pump can provide current is shown in the Electrical Characteris- tics table. GLA, GLB, and GLC Pins These are the low-side gate drive outputs for the external N-channel MOSFETs. External resistors between the gate drive output and the gate connection to the FET (as close as possible to the FET) can be used to control the slew rate seen at the gate, thereby providing some control of the di/dt and dv/dt of the SA, SB, and SC outputs. GLx going high turns on the upper half of the drive, sourcing current to the gate of the low- side FET in the external power bridge, turning it on. GLx going low turns on the lower half of the drive, sinking current from the external FET gate circuit to the LSS pin, turning off the FET. SA, SB, and SC Pins Directly connected to the motor, these terminals sense the voltages switched across the load. These terminals are also connected to the negative side of the bootstrap capacitors and are the negative supply connections for the floating high-side drives. The discharge current from the high-side FET gate capacitance flows through these connections, which should have low impedance circuit connections to the FET bridge. GHA, GHB, and GHC Pins These terminals are the high-side gate drive outputs for the external N-channel FETs. External resistors between the gate drive output and the gate connection to the FET (as close as possible to the FET) can be used to control the slew rate seen at the gate, thereby controlling the di/dt and dv/dt of the SA, SB, and SC outputs. GHx going high turns on the upper half of the drive, sourcing current to the gate of the high-side FET in the external motor-driving bridge, turning it on. GHx going low turns on the lower half of the drive, sinking current from the external FET gate circuit to the corresponding Sx pin, turning off the FET. CA, CB, and CC Pins These are the high-side connections for the bootstrap capacitors and are the positive supply for the high-side gate drives. The bootstrap capacitors are charged to approximately VREG when the associated output Sx terminal is low. When the Sx output swings high, the charge on the bootstrap capacitor causes the voltage at the corresponding Cx terminal to rise with the output to provide the boosted gate voltage needed for the high-side FETs. LSS Pin This is the low-side return path for discharge of the capacitance on the FET gates. It should be tied directly to the common sources of the low-side external FETs through an inde- pendent low impedance connection. RDEAD Pin This pin controls internal generation of dead time during FET switching. • When a resistor greater than 3 kΩ is connected between RDEAD and AGND, cross-conduction is prevented by the gate drive circuits, which introduce a dead time, tDEAD, between switching one FET off and the complementary FET on. The dead time is derived from the resistor value connected between the RDEAD and AGND pins. • When RDEAD is connected directly to VDD, cross-conduction is prevented by the gate drive circuits. In this case, tDEAD defaults to a value of 6 μs typical. • When RDEAD is connected directly to AGND, internal dead time generation is disabled. This allows dead times of any duration to be determined by the external controller through the relative timing of the phase logic control inputs, xHI and xLO. Note that when using an external controller to determine the dead time, care must be taken to ensure that unintentional shorts across the supply are avoided. Logic Control Inputs Low voltage-level digital inputs provide control for the gate drives. The input logic is shown in table 1. These logic inputs can be driven from either 3.3 or 5 V logic. All have a nominal hysteresis of 500 mV to improve noise perfor- mance. AHI, BHI, CHI, ALO, BLO, and CLO Pins These are the phase control inputs. The xHI inputs control the high-side drives and the xLO inputs control the low-side drives. Internal lockout logic ensures that the high-side output drive and low-side output drive cannot be active simultaneously, except when RDEAD is connected to AGND and at the same time CCEN is set high, as described in the CCEN pin section. PWMH and PWML Pins These inputs can be used to externally control motor torque and speed. • Setting PWMH low turns off active high-side drives and turns on the complementary low-side drives. This provides high- side–chopped slow-decay PWM with synchronous rectification. |
Similar Part No. - A4933_16 |
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Similar Description - A4933_16 |
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