Single Phase Fan Pre-Driver

A4930

5

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

VREG5

This pin should be decoupled with a 0.1 μF capacitor

to ground. VREG5 can supply up to 15 mA, which can used to

power the external Hall element.

VREG8

This pin should be decoupled with a 0.1 μF capacitor to

ground. VREG8 is used to power the low-side gate drive circuits.

Charge Pump

The charge pump is used to generate a supply

is internally monitored, and in the case of a fault condition, the

outputs of the device are disabled.

Lock Detect

The IC detects a locked rotor condition by checking

to ensure that the FG output signal is continuously changing. The

length of time allowed for a stoppage before evaluating a locked

duces a triangle waveform with a frequency that is linearly related

of this triangle waveform, and its value can be calculated as:

(1)

the appropriate source driver and hold both sink drivers on. The

circuit will automatically retry with a 15:1 ratio of off-time to on-

time. An RD pin logic high indicates this fault condition.

Current Limit and Soft Start

To minimize demand on the

power supply, peak current is controlled. Initially, with the fan

at a stand-still, the turn-on of the bridge results in current rising

according to the L/R time constant of the motor. To prevent over-

stress, this peak current is regulated by an internal PWM control

circuit. When the outputs of the full-bridge are turned on, current

increases in the motor winding until it reaches a value given by:

(2)

within the range of 200 to 500 mV, according to the relationship:

(3)

At the trip point, the sense comparator resets the source enable

latch, turning off the source driver. At this point, load inductance

causes the current to recirculate for 50 μs.

A soft start capacitor, CSS, can be connected to the SS pin to set

the rate for slowly ramping-up the load current to the maximum

value, according to the relationship:

(4)

In this case the current limit will likely not be achieved and there

will be less demand on the input power supply. If this feature is

not utilized, the SS pin should be left open.

Synchronous Rectification

When a PWM off-cycle is triggered,

load current recirculates. The A4930 synchronous rectification

feature turns on the appropriate MOSFETs during current decay,

driver.

TSD

If the die temperature exceeds approximately 165°C, the

outputs will be disabled until the internal temperature falls below

a hysteresis level of 15°C.

Shutdown

In the event of a fault due to excessive junction

temperature, or low voltage on VCP or VBB, the outputs of

the device are disabled until the fault condition is removed. At

power-up the UVLO circuit disables the drivers until the UVLO

threshold is reached.

CPWM

This capacitor sets the frequency of the internal PWM

circuit. The value is typically from 15 to 30 kHz.

PWM

The IC accepts a direct input PWM signal with a level in

the range from 0 to 6 V. The duty cycle, DC, of the input to this

pin is converted to an analog voltage that is output on the SIN

terminal as follows:

(5)

If the PWM input is not used, then leave this pin open circuit.

Direct external PWM control can be utilized by applying the

signal to the SIN input (refer to the Applications Information sec-

tion). This can be implemented to create different PWM input to

PWM output transfer functions.

Functional Description