TPS2346

SLUS529 – MAY 2002

6

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pin descriptions

AGND: Analog ground reference for the device.

CPGND: Charge pump ground pin for the device.

CPUMP: Charge pump resevoir capacitor connection. An external capacitor of value 0.1

µF to 1 µF must be

connected between this pin and CPGND. The capacitor provides charge storage for the internal charge pump

for gate drive of the external N-channel FETs in line with the three positive-voltage loads.

CS1, CS2, CS3: These pins tie to the load side of the Channel 1, 2, and 3 current sense resistors, respectively.

They are used in conjunction with the VIN1, VIN2 and VIN3 inputs to provide load current magnitude information

to each of the positive rail LCAs.

CS4: This pin ties to the more positive side of the Channel 4 current sense resistor (common with the pass FET

source). It is used in conjunction with the VIN4 input to provide Channel 4 current magnitude information to the

negative rail LCA.

ENABLE: Logic low enable input for back-end power. This pin ties to the module enable input at the plug-in

slot. When the input supplies are above the device minimums, and this pin is asserted low the TPS2346 begins

the sequential ramp–up of the back-end supplies. Pulling this input high (>2 V) turns off power to the back-end

planes, and puts the TPS2346 into low-power sleep mode.

GATE1, GATE2, GATE3, GATE4: Gate drive outputs for the Channel 1 through Channel 4 pass FETs,

respectively. The gates are driven according to the supply voltage, enable, sequence programming and load

current conditions of the add-in board.

IRAMP: Current ramp programming pin. A capacitor connected between this pin and ground determines the

maximum slew rate of the load current during ramp-up and ramp-down of the three positive back-end voltages.

This same capacitor is also used to establish the time limit for ramping each of the supply outputs.

PG: Open-drain output asserted low to signal a back-end power-good condition. During a turn-on event, if each

of the load rails ramps up successfully to within the factory-programmed tolerances of the undervoltage (UV)

and overvoltage (OV) comparators, this output is subsequently asserted low. The output is false when back-end

power is not enabled, if any of the back-end voltages is not within its UV/OV window, as a result of an overcurrent

indication on any supply controller, or as a result of a fault timeout during linear ramp-up of any load voltage.

PRECHG: Bias supply of 1 V for bus signal precharge. During plug-in insertion and extraction events, this

output provides a bias supply that can be used to precharge the signal and control lines of the system’s

address/data bus.

RGND: Reference ground input for the device.

VIN1: Channel 1 supply (5.15-V) input voltage sense. This pin is connected to the 5.15-V power supply input

to the add-in card. The supply potential is tested against the undervoltage limits prior to ramping voltage to the

back-end 5.15-V plane. The input supply also serves as the reference potential for the internally generated

current limit (IMAX) reference of the Channel 1 LCA. This pin also serves as the VCC supply for the TPS2346.

VIN2: Channel 2 supply (5-V) input voltage sense. This pin is connected to the 5-V power supply input to the

add-in card. The supply potential is tested against the undervoltage limits prior to ramping voltage to the

back-end 5-V plane. The input supply also serves as the reference potential for the internally generated current

limit (IMAX) reference of the Channel 2 LCA. This pin also serves as the supply input for the precharge bias

output.

VIN3: Channel 3 supply (3.3-V) input voltage sense. This pin is connected to the 3.3-V power supply input to

the add-in card. The supply potential is tested against the undervoltage limits prior to ramping voltage to the

back-end 3.3-V plane. The input supply also serves as the reference potential for the internally generated

current limit (IMAX) reference of the Channel 3 LCA.