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A3921 Datasheet(PDF) 8 Page - Allegro MicroSystems |
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A3921 Datasheet(HTML) 8 Page - Allegro MicroSystems |
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8 / 21 page  Automotive Full Bridge MOSFET Driver A3921 8 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com In some applications a safety resistor is added between the gate and source of each FET in the bridge. When a high-side FET is held in the on-state, the current through the associated high-side gate-source resistor (RGSH) is provided by the high-side drive and therefore appears as a static resistive load on the top-off charge pump. The minimum value of RGSH for which the top-off charge pump can provide current is shown in the Electrical Characteris- tics table. GLA and GLB Pins These are the low-side gate drive outputs for the external N-channel MOSFETs. External resistors between the gate drive output and the gate connection to the FET (as close as possible to the FET) can be used to control the slew rate seen at the gate, thereby providing some control of the di/dt and dv/dt of the SA and SB outputs. GLx going high turns on the upper half of the drive, sourcing current to the gate of the low-side FET in the external power bridge, turning it on. GLx going low turns on the lower half of the drive, sinking current from the external FET gate circuit to the LSS pin, turning off the FET. SA and SB Pins Directly connected to the motor, these terminals sense the voltages switched across the load. These terminals are also connected to the negative side of the bootstrap capacitors and are the negative supply connections for the floating high-side drives. The discharge current from the high-side FET gate capaci- tance flows through these connections, which should have low impedance circuit connections to the FET bridge. GHA and GHB Pins These terminals are the high-side gate drive outputs for the external N-channel FETs. External resistors between the gate drive output and the gate connection to the FET (as close as possible to the FET) can be used to control the slew rate seen at the gate, thereby controlling the di/dt and dv/dt of the SA and SB outputs. GHx going high turns on the upper half of the drive, sourcing current to the gate of the high-side FET in the external motor-driving bridge, turning it on. GHx going low turns on the lower half of the drive, sinking current from the external FET gate circuit to the corresponding Sx pin, turning off the FET. CA and CB Pins These are the high-side connections for the bootstrap capacitors and are the positive supply for the high-side gate drives. The bootstrap capacitors are charged to approxi- mately VREG when the associated output Sx terminal is low. When the Sx output swings high, the charge on the bootstrap capacitor causes the voltage at the corresponding Cx terminal to rise with the output to provide the boosted gate voltage needed for the high-side FETs. LSS Pin This is the low-side return path for discharge of the capacitance on the FET gates. It should be tied directly to the common sources of the low-side external FETs through an inde- pendent low impedance connection. RDEAD Pin This pin controls internal generation of dead time during FET switching. • When a resistor greater than 3 kΩ is connected between RDEAD and AGND, cross-conduction is prevented by the gate drive circuits, which introduce a dead time, tDEAD, between switching one FET off and the complementary FET on. The dead time is derived from the resistor value connected between the RDEAD and AGND pins. • When RDEAD is connected directly to V5, cross-conduction is prevented by the gate drive circuits. In this case, tDEAD defaults to a value of 6 μs typical. Logic Control Inputs Four low-voltage level digital inputs provide control for the gate drives. These logic inputs all have a nominal hysteresis of 500 mV to improve noise performance. They are used together to provide fast decay or slow decay with high-side or low-side recirculation. They also provide brake, coast, and sleep modes as defined in tables 1 and 2. PWMH and PWML Pins These inputs can be used to control current in the power bridge. PWMH provides high-side chopping and PWML provides low-side chopping. When used together they control the power bridge in fast decay mode. The PWM options are provided in table 2. • Setting PWMH low turns off active high-side drives. This provides high-side–chopped slow-decay PWM. • Setting PWML low turns off active low-side drives. This provides low-side–chopped slow-decay PWM. • PWMH and PWML may also be connected together and driven with a single PWM signal. This provides fast-decay PWM. PHASE Pin The state of the PHASE pin determines the positive direction of load current (see table 1). The PHASE pin can also be used as a PWM input when full four-quadrant control (fast decay synchronous rectification) is required (see table 2). SR Pin This enables or disables synchronous rectification. When SR is high, synchronous rectification is enabled during the PWM off time. PWM off time is present when there is a low on either |
Similar Part No. - A3921_16 |
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Similar Description - A3921_16 |
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