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UCD7230RGWTG4 Datasheet(PDF) 11 Page - Texas Instruments |
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UCD7230RGWTG4 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 26 page 0 1 2 4 5 6 OUT2 - V 0 1.0 2.0 3.0 4.0 5.0 3 0.5 1.5 2.5 3.5 4.5 Sink Current VDD = 12 V Sink Current VDD = 5 V Source Current VDD = 12 V Source Current VDD = 5 V OUT2 SOURCE/SINK CURRENT vs OUT2 VOLTAGE 0 1 2 4 5 6 OUT1 - SW - V 0 1.0 2.0 3.0 4.0 5.0 3 0.5 1.5 2.5 3.5 4.5 Sink Current VDD = 12 V Sink Current VDD = 5 V Source Current VDD = 12 V Source Current VDD = 5 V OUT1 SOURCE/SINK CURRENT vs OUT1 VOLTAGE WITH RESPECT TO SW VOLTAGE UCD7230 www.ti.com SLUS741D – NOVEMBER 2006 – REVISED JANUARY 2010 Driver Stages The driver outputs utilize Texas Instruments’ TrueDrive™ architecture, which delivers rated current into the gate of a MOSFET when it is most needed, during the Miller plateau region of the switching transition. This provides best switching speeds and reduces switching losses. TrueDrive™ consists of pull-up/ pull-down circuits using bipolar and MOSFET transistors in parallel. This hybrid output stage also allows relatively constant current sourcing even at reduced supply voltages. The low-side high-current output stage of the UCD7230 device is capable of sourcing 1.7-A and sinking 3.5-A current pulses and swings from PVDD to PGND. The high-side floating output driver is capable of sourcing 2.2-A and sinking 3.5-A peak-current pulses. This ratio of gate currents, common to synchronous buck applications, minimizes the possibility of parasitic turn on of the low-side power MOSFET due to dv/dt currents during the rising edge switching transition. See the typical curves of sink and source current in Figure 3 and Figure 4 below. If further limiting of the rise or fall times to the power device is desired, an external resistance can be added between the output of the driver and the power MOSFET gate. The external resistor also helps remove power dissipation from the driver. Driver outputs follow IN and SRE as previously described provided that VDD and 3V3 are above their respective under-voltage lockout thresholds. When the supplies are insufficient, the chip holds both OUT1 and OUT2 low. It is worth reiterating the need mentioned in the supply section for sound high frequency design techniques in the circuit board layout and bypass capacitor selection and placement. Some applications may generate excessive ringing at the switch-inductor node. This ringing can drag SW to negative voltages that might cause functional irregularities. To prevent this, carefull board layout and appropriate snubbing are essential. In addition, it may be appropriate to couple SW to the inductor with a 1- Ω resistor, and then bypass SW to PGND with a low impedance Schottky diode. Figure 3. Figure 4. Copyright © 2006–2010, Texas Instruments Incorporated 11 Product Folder Link(s): UCD7230 Obsolete Device |
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