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CD54HC533 Datasheet(PDF) 6 Page - Texas Instruments

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Part No. CD54HC533
Description  High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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 6 page
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6
Enable Times
(HC533)
tPZH, tPZL
CL = 50pF
2
-
150
190
225
ns
4.5
-
30
38
45
ns
6
-
26
33
38
ns
CL = 15pF
5
12
-
-
-
ns
Disable Times
(HC533)
tPHZ, tPLZ
CL = 50pF
2
-
150
190
225
ns
4.5
-
30
38
45
ns
6
-
26
33
38
ns
CL = 15pF
5
12
-
-
-
ns
Enable and Disable Times
(HC563)
tPZH, tPZL,
tPHZ, tPLZ
CL = 50pF
2
-
150
190
225
ns
4.5
-
30
38
45
ns
6
-
26
33
38
ns
CL = 15pF
5
12
-
-
-
ns
Input Capacitance
CI
--
-
10
10
10
pF
Three-State Output
Capacitance
CO
--
-
20
20
20
pF
Power Dissipation
Capacitance
(Notes 3, 4)
CPD
-
5
42
-
-
-
pF
HCT TYPES
Propagation Delay,
Data to Qn
(HC/HCT533)
tPLH, tPHL
CL = 50pF
4.5
-
34
43
51
ns
CL = 15pF
5
14
-
-
-
ns
Propagation Delay,
Data to Qn
(HC/HCT563)
tPLH, tPHL
CL = 50pF
4.5
-
30
38
45
ns
CL = 15pF
5
12
-
-
-
ns
Propagation Delay,
LE to Qn
(HC/HCT533)
tPLH, tPHL
CL = 50pF
4.5
-
38
48
57
ns
CL = 15pF
5
16
-
-
-
ns
Propagation Delay,
LE to Qn
(HC/HCT563)
tPZL, tPZH
CL = 50pF
4.5
-
35
44
53
ns
CL = 15pF
5
14
-
-
-
ns
Enable Times
(HC/HCT533)
tPLZ, tPZH
CL = 50pF
4.5
-
35
44
53
ns
CL = 15pF
5
14
-
-
-
ns
Disable Times
(HC/HCT533)
tTLH, tTHL
CL = 50pF
4.5
-
30
38
45
ns
CL = 15pF
5
12
-
-
-
ns
Enable and Disable Times
(HC/HCT563)
tPZH, tPZL,
tPHZ, tPLZ
CL = 50pF
4.5
-
35
44
53
ns
CL = 15pF
5
14
-
-
-
ns
Input Capacitance
CI
--
-
10
10
10
pF
Power Dissipation
Capacitance
(Notes 3, 4)
CPD
-
5
42
-
-
-
pF
NOTES:
3. CPD is used to determine the no-load dynamic power consumption, per latch.
4. PD (total power per latch) = CPD VCC
2 f
i + Σ CL VCC
2 f
o where fi = Input Frequency, fo = Output Frequency, CL = Output Load
Capacitance, VCC = Supply Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC (V)
25oC
-40oC TO 85oC
-55oC TO
125oC
UNITS
TYP
MAX
MAX
MAX
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563




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