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BQ29312PWR Datasheet(PDF) 7 Page - Texas Instruments

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Part # BQ29312PWR
Description  THREE AND FOUR CELL LITHIUM-LON ORLITHIUM-POLYMER BATTERY PROTECTION AFE
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

BQ29312PWR Datasheet(HTML) 7 Page - Texas Instruments

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bq29312
SLUS546D − MARCH 2003 − REVISED SEPTEMBER 2004
www.ti.com
7
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
BAT
DSG
VC1
VC2
VC3
VC4
VC5
SR1
SR2
WDI
CELL
GND
OD
PMS
PACK
ZVCHG
CHG
SLEEP
REG
TOUT
XALERT
GND
SDATA
SCLK
PW PACKAGE
(TOP VIEW)
VC3
VC4
SR2
SR1
VC5
XALERT
REG
TOUT
ZVCHG
VC2
SLEEP
CHG
RGE PACKAGE
(TOP VIEW)
Terminal Functions
TERMINAL
NO.
NAME
DESCRIPTION
NO.
QFN
PW
DESCRIPTION
1
VC2
BAT
Diode protected BAT+ terminal and primary power source.
2
VC3
DSG
Push-pull output discharge FET gate drive
3
VC4
VC1
Sense voltage input terminal for most positive cell and balance current input for most positive cell.
4
VC5
VC2
Sense voltage input terminal for second most positive cell, balance current input for second most positive cell
and return balance current for most positive cell.
5
SR1
VC3
Sense voltage input terminal for third most positive cell, balance current input for third most positive cell and
return balance current for second most positive cell.
6
SR2
VC4
Sense voltage input terminal for least positive cell, balance current input for least positive cell and return balance
current for third most positive cell.
7
WDI
VC5
Sense voltage input terminal for most negative cell, return balance current for least positive cell.
8
CELL
SR1
Current sense positive terminal when charging relative to SR2
Current sense negative terminal when discharging relative to SR2
9
GND
SR2
Current sense terminal
10
SCLK
WDI
Digital input that provides the timing clock for the OC and SC delays and also acts as the watchdog clock.
11
SDATA
CELL
Output of scaled value of the measured cell voltage.
12
GND
GND
Analog ground pin and negative pack terminal
13
XALERT
SCLK
Open-drain bidirectional serial interface clock with internal 10 k
Ω pull-up to V(REG).
14
TOUT
SDATA
Open-drain bidirectional serial interface data with internal 10 k
Ω pull-up to V(REG).
15
REG
GND
Connect to GND
16
SLEEP
XALERT
Open-drain output used to indicate status register changes. With internal 100 k
Ω pull-up to V(REG)
17
CHG
TOUT
Provides thermistor bias current
18
ZVCHG
REG
Integrated 3.3-V regulator output
19
PACK
SLEEP
This pin is pulled up to V(REG) internally, open or H level makes Sleep mode
20
PMS
CHG
Push-pull output charge FET gate drive
21
OD
ZVCHG
The ZVCHG FET drive is connected here
22
BAT
PACK
PACK positive terminal and alternative power source
23
DSG
PMS
0-V charge configuration select pin, CHG terminal ON/OFF is determined by this pin.
24
VC1
OD
NCH FET open drain output


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