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TPD4E110DPWR Datasheet(PDF) 10 Page - Texas Instruments

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Part # TPD4E110DPWR
Description  4 Channel Protection Solution for Super-Speed (Up to 6 GBPS) Interface
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPD4E110DPWR Datasheet(HTML) 10 Page - Texas Instruments

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USB 3.0 Type A
Connector PCB
Footprint
TPD4E110DPW
1
2
TPD4E110
SLVSC54B – JULY 2013 – REVISED APRIL 2014
www.ti.com
10 Layout
10.1 Layout Guidelines
The optimum placement is as close to the connector as possible.
EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
Electric fields tend to build up on corners, increasing EMI coupling.
10.2 Layout Example
10.2.1 Single Layer Routing
PCB manufacturing technologies allowing 2.8 mil (0.071 mm) clearances can route two Super-Speed data line
pairs through TPD4E110 on a single layer.
Figure 15. Example Layout for USB 3.0 Type A connector using two TPD4E110s
In Figure 15, Figure 16 and Figure 17 an example layout shows the use of two TPD4E110s to protect the USB
3.0 port. TPD4E110 Number 1 is protecting the two Super-Speed data pairs used for Super Speed data transfer,
and TPD4E110 Number 2 protects the USB 2.0 D+/D– Hi-Speed data lines. Number 2 uses two channels to
protect each line in the pair, thus affording a more robust protection and simpler layout.
10
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Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: TPD4E110


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