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A1454KLETR-2F-T Datasheet(PDF) 6 Page - Allegro MicroSystems |
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A1454KLETR-2F-T Datasheet(HTML) 6 Page - Allegro MicroSystems |
6 / 15 page 3V Hall Effect Linear Sensor with I2C Output A1454 6 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com PRIMARY REGISTERS Customer Accessible Registers The following table shows registers that are customer accessible and can be read/written using the I2C protocol. Table 1: Customer Accessible Registers Address Name Bit Field 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0X1D Temp Out [11:0] Temperature Sensor Output 0X1F Output [11:0] Sensor Output 0X20 Sleep [)] Sensor Output The A1454 provides a 12 bit digital output that is proportional to the magnetic field applied normally to the hall element. Table 2: Output [11:0], Address 0x1F, Bit Definition Table Bits Address Name Value Description R/W Default 11:0 0x1F Output 0/1 (for each bit) 12-bit signed signal proportional to field strength intensity. 0G is denoted by 12’b0 value. R – Temperature Sensor Output The A1454 provides a 12-bit digital output that is proportional to the junction temperature of the hall-sensor IC. Table 3: Temp Out [11:0], Address 0x1D, Bit Definition Table Bits Address Name Value Description R/W Default 11:0 0x1D Temp Out 0/1 (for each bit) 12-bit signed signal proportional to temperature. 25C is denoted by a 12’b0 value. Temperature Slope is ~ 8 LSB/ºC. R – Table 4: Sleep [0], Address 0x20, Bit Definition Table Bits Address Name Value Description R/W Default 0 0x20 Sleep Mode 0/1 Sleep Mode Enable Bit R/W – Sleep Mode The 1454 supports a sleep mode where numerous sub-systems are powered. To enter sleep mode, the user sets the sleep con- trol bit. To awake from sleep mode the user clears the sleep bit. Since the I²C logic uses SCL as its clock source and the sleep bit implemented in the SCL clock domain, the system clock does not need to be operational for the sleep output to be cleared. Within a period of about 50 µs after clearing the sleep bit, the system clock will be operational, and the A1454 IC will respond to I2C commands. Furthermore, within a period of about 150 µs after clearing the sleep bit, the A1454 will be able to provide a digital output that is fairly accurate, but not temperature compensated. Lastly, within a period of about 500 µs after clearing the sleep bit, the A1454 will be able to provide an output value that is accurate to within the device accuracy specifications. Therefore, a design trade-off can be made between wake-up time, and accuracy of output, based on the specific system-level requirements. |
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