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TNETE2004PBE Datasheet(PDF) 6 Page - Texas Instruments |
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TNETE2004PBE Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 47 page  TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions controller interface TERMINAL † NAME NO. I/O† DESCRIPTION NAME 120 128 AUTONEG 74 82 I Auto-negotiation. When high, AUTONEG enables auto-negotiation on all four PHYs. Auto-negotiation takes place only after a reset or when a link is reestablished. AUTONEG can be overridden from the MDI. COL0 COL1 COL2 COL3 117 34 56 93 127 40 62 103 O Collision sense. When asserted, COL0–COL3 indicates that PHY0–PHY3 sensed a network collision. The active level is set by the compatibility pins (see Table 2) or by setting the correct bits in pin-polarity register 0x16 (see Figure 17). Functions are described in Table 13. CRS0 CRS1 CRS2 CRS3 2 29 61 88 4 35 67 98 O Carrier sense. When asserted, CRS0–CRS3 indicates that PHY0–PHY3 is receiving a frame carrier signal. The active level is set by the compatibility pins (see Table 2) or by setting the correct bits in pin-polarity register 0x16 (see Figure 17). Functions are described in Table 13. DUPLEX0 DUPLEX1 DUPLEX2 DUPLEX3 5 26 64 85 7 32 70 95 O/D Duplex mode. When DUPLEX0–DUPLEX3 is high, PHY0–PHY3 operates in full-duplex mode. When DUPLEX0–DUPLEX3 is low, PHY0–PHY3 operates in the half-duplex mode. There is an internal weak drive on DUPLEX0–DUPLEX3 that pulls DUPLEX0–DUPLEX3 if auto-negotiation chooses the full-duplex mode, or if full duplex is chosen by writing to an MDI register. By connecting DUPLEX0–DUPLEX3 GND or VDD, this weak drive is overridden, and the type of duplex mode is permanently set, ignoring any auto-negotiation decisions or values written to the appropriate MDI registers. To set duplex mode, connect the auto-negotiation pin low. (This turns off auto-negotiation.) LINK0 LINK1 LINK2 LINK3 4 27 63 86 6 33 69 96 O Link status. When LINK0–LINK3 is high, it indicates that PHY0–PHY3 has determined that a valid 10BASE-T link has been established. When low, LINK0–LINK3 indicates that the link has not been established. LOOPBACK 16 20 I Loopback. When low, LOOPBACK enables internal loopback in all four PHYs. When asserted, data is internally wrapped within each PHY and does not appear on the network. While in the looped-back state, all network lines are placed in a noncontentious state. LOOPBACK can be overridden by the MDI registers. RXCLK0 RXCLK1 RXCLK2 RXCLK3 1 31 59 89 3 37 65 99 O Receive clock. Receive clock source for the receive data output RXD0–RXD3. Data is valid on RXD0–RXD3 on the edges of RXCLK0–RXCLK3 specified by the currently set compatibility mode (see Table 2) or by setting the correct bits in pin-polarity register 0x16 (see Figure 17). Functions are described in Table 13. RXD0 RXD1 RXD2 RXD3 3 28 62 87 5 34 68 97 O Receive data. Bit-wise serial-data output from PHY0–PHY3. SQE 75 83 I Signal quality error. When high, SQE causes each PHY to simulate a collision condition at the end of each frame transmission to test functionality of the collision-detect circuitry. SQE is overridden by SQEEN (see Table 8). SQE must be set high to interface with the TNETX3150. TXCLK 101 111 O Transmit clock. TXCLK is shared by all PHYs to clock in transmit data. Data is valid on TXD0-TDX3 on the edges of TXCLK specified by the currently set compatibility mode (see Table 2) or by setting the correct bits in pin-polarity register 0x16 (see Figure 17). Functions are described in Table 13. TXD0 TXD1 TXD2 TXD3 119 32 58 91 1 38 64 101 I Transmit data. Serial-data input to PHY0–PHY3. TXEN0 TXEN1 TXEN2 TXEN3 118 33 57 92 128 39 63 102 I Transmit enable. Assert TXEN0–TXEN3 active to indicate that valid transmit data is on TXD0–TXD3. The active level is set by the compatibility pins (see Table 2) or by setting the correct pins in pin-polarity register 0x16 (see Figure 17). Functions are described in Table 13. † I = input, O = output, O/D = open-drain output |
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