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ASR8600 Datasheet(PDF) 7 Page - AMIC Technology |
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ASR8600 Datasheet(HTML) 7 Page - AMIC Technology |
7 / 14 page ASR8600 PRELIMINARY (March, 2015, Version 0.0) 6 AMIC Technology Corp. I2C Protocol The bus interface and control are accomplished through an I2C compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the IC and the master at clock rate up to 400k Hz. The devices support the 7-bit I2C addressing protocol and 8-bit register address and data byte. The I2C standard provides for three types of bus transaction: read, write, and a combined protocol. During a write operation, after (slave_address + R/W) byte, the first byte written is a register address followed by data byte. If a read command is issued, the register address from the previous command will be used for data access. In a combined protocol, the first byte written is the register address followed by reading a series of data bytes. ASR8600 slave address is 1001010X, which 0x94 is Write to ASR8600, and 0x95 is Read from ASR8600 . The I2C bus protocol follows Philip TM (now NXP company) I2C specification. For a complete description of I2C protocol, please refer to NXP I2C design specification. I2C Protocols S Slave Address W A Register Address A Data Byte A P ... 17 1 1 8 1 8 1 1 I2C Write Protocol S Slave Address R A Data Byte A Data Byte A P ... 17 1 1 8 1 8 1 1 I2C Read Protocol S Slave Address W A Register Address A A R 17 1 1 8 11 1 I2C Read Protocol - Combined Format SR Slave Address 7 A N P R S SR W ... Acknowledge (0) Not Acknowledge (1) Stop Condition Read (1) Start Condition Repeated Start Condition Write (0) Condition of protocol Master-to-Slave Slave-to-Master Data Byte A 1 8 ... ... 1 1 Data Byte N P 8 Data Byte A 1 8 Timing Diagrams t(BUF) VIH VIL VIH VIL t(LOW) t(R) t(HDSTA) t(HDDAT) t(HIGH) t(F) t(SUSTA) t(SUDAT) t(SUSTO) SCL SDA P S S P Stop Condition Start Condition I2C Bus Timing Characteristics Symbol Parameter Min. Typ. Max. Unit f(SCL) Serial-Clock Frequency 0 400 KHz t(HIGH) Clock High Period 0.6 µs t(LOW) Clock Low Period 1.3 µs T(R) Clock/Data Rise Time 100 ns T(F) Clock/Data Fall Time 100 ns t(SUDAT) Data Setup Time 0.1 µs t(HDDAT) Data Hold Time 0 µs t(BUF) Bus Free Time Between STOP and START 1.3 µs t(HDSTA) Hold Time (Repeated) Start Condition 0.6 µs t(SUSTA) Repeated Start Condition Setup Time 0.6 µs t(SUSTO) Stop Condition Setup Time 0.6 µs t(SP) Pulse Width of Suppressed Spike 0 50 ns |
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