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TMS320F28066PNT Datasheet(PDF) 3 Page - Texas Instruments |
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TMS320F28066PNT Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 177 page  CLA Bus DMA Bus DMA Bus 16-bit Peripheral Bus 32-bit Peripheral Bus Memory Bus A7:0 B7:0 Memory Bus ADC 0-wait Result Regs ADC COMP + DAC COMP1OUT COMP2OUT COMP3OUT COMP1A COMP2A COMP3A COMP1B COMP2B COMP3B Boot-ROM (32K 16) (0-wait, Non-Secure) ´ TRST TCK, TDI, TMS TDO XCLKIN LPM Wakeup 3 Ext. Interrupts X1 X2 XRS M0 SARAM (1K 16) (0-wait, Non-Secure) ´ M1 SARAM (1K 16) (0-wait, Non-Secure) ´ L5 DPSARAM (8K 16) (0-wait, Non-Secure) DMA RAM0 ´ L6 DPSARAM (8K 16) (0-wait, Non-Secure) DMA RAM1 ´ L7 DPSARAM (8K 16) (0-wait, Non-Secure) DMA RAM2 ´ L8 DPSARAM (8K 16) (0-wait, Non-Secure) DMA RAM3 ´ L0 DPSARAM (2K 16) (0-wait, Secure) CLA Data RAM2 ´ L1 DPSARAM (1K 16) (0-wait, Secure) CLA Data RAM0 ´ L2 DPSARAM (1K 16) (0-wait, Secure) CLA Data RAM1 ´ L3 DPSARAM (4K 16) (0-wait, Secure) CLA Program RAM ´ L4 SARAM (8K 16) (0-wait, Secure) ´ Code Security Module (CSM) PSWD OTP 1K 16 Secure ´ FLASH 128K 16 8 equal sectors Secure ´ 64K 16 ´ PUMP OTP/Flash Wrapper 32-bit Peripheral Bus USB-0 GPIO Mux SCI-A SCI-B (4L FIFO) SPI-A SPI-B (4L FIFO) I2C-A (4L FIFO) 32-bit Peripheral Bus (CLA accessible) ePWM1 to ePWM8 HRPWM (8ch) McBSP-A 32-bit Peripheral Bus (CLA accessible) eCAP1 eCAP2 eCAP3 eQEP1 eQEP2 32-bit Peripheral Bus HRCAP1 HRCAP2 HRCAP3 HRCAP4 eCAN-A (32-mbox) CLA + Message RAMs DMA 6-ch C28x 32-bit CPU FPU VCU OSC1, OSC2, Ext, PLLs, LPM, WD, CPU Timer 0, CPU Timer 1, CPU Timer 2, PIE 3 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698F – NOVEMBER 2010 – REVISED MARCH 2016 Submit Documentation Feedback Product Folder Links: TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Device Overview Copyright © 2010–2016, Texas Instruments Incorporated 1.4 Functional Block Diagram Figure 1-1 shows a functional block diagram of the device. A. Not all peripheral pins are available at the same time due to multiplexing. Figure 1-1. Functional Block Diagram |
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