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TMS320UC5402 Datasheet(PDF) 11 Page - Texas Instruments |
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TMS320UC5402 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 77 page  Introduction 1 April 1999 − Revised October 2008 SPRS096C 1 Introduction This section describes the main features of the TMS320UC5402, lists the pin assignments, and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging. NOTE: This data manual is designed to be used in conjunction with theTMS320C54x DSP Functional Overview (literature number SPRU307). 1.1 Features D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus D 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators D 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation D Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator D Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle D Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) D Data Bus With a Bus-Holder Feature D Extended Addressing Mode for 1M × 16-Bit Maximum Addressable External Program Space D 4K x 16-Bit On-Chip ROM D 16K x 16-Bit On-Chip Dual-Access RAM D Single-Instruction-Repeat and Block-Repeat Operations for Program Code D Block-Memory-Move Instructions for Efficient Program and Data Management D Instructions With a 32-Bit-Long Word Operand D Instructions With Two- or Three-Operand Reads D Arithmetic Instructions With Parallel Store and Parallel Load D Conditional Store Instructions D Fast Return From Interrupt D On-Chip Peripherals − Software-Programmable Wait-State Generator and Programmable Bank Switching − On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source − Two Multichannel Buffered Serial Ports (McBSPs) − Enhanced 8-Bit Parallel Host-Port Interface (HPI8) − Two 16-Bit Timers − Six-Channel Direct Memory Access (DMA) Controller D Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes D CLKOUT Off Control to Disable CLKOUT D On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1† (JTAG) Boundary Scan Logic D 12.5-ns Single-Cycle Fixed-Point Instruction Execution Time (80 MIPS) D 1.8-V Core Power Supply D 1.8-V to 3.6-V I/O Power Supply Enables Operation With a Single 1.8-V Supply or with Dual Supplies D Available in a 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix) D Available in a 144-Ball MicroStar Ball Grid Array (BGA) (GGU Suffix) TMS320C54x and MicroStar BGA are trademarks of Texas Instruments. All trademarks are the property of their respective owners. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. |
Similar Part No. - TMS320UC5402_09 |
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Similar Description - TMS320UC5402_09 |
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