TMS44400, TMS44400P, TMS46400, TMS46400P

1048576-WORD BY 4-BIT

DYNAMIC RANDOM-ACCESS MEMORIES

SMHS562C – MAY 1995 – REVISED NOVEMBER 1996

6

POST OFFICE BOX 1443

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

PARAMETER

TEST

CONDITIONS

’44400 - 60

’44400P - 60

’44400 - 70

’44400P - 70

’44400 - 80

’44400P - 80

UNIT

CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

VOH

High-level output voltage

IOH = – 5 mA

2.4

2.4

2.4

V

VOL

Low-level output voltage

IOL = 4.2 mA

0.4

0.4

0.4

V

II

Input current (leakage)

VCC = 5.5 V,

VI = 0 V to 6.5 V,

All others = 0 V to VCC

± 10

± 10

± 10

µA

IO

Output current (leakage)

VCC = 5.5 V,

VO = 0 V to VCC,

CAS high

± 10

± 10

± 10

µA

ICC1

Read- or write-cycle current

(see Note 3)

VCC = 5.5 V,

Minimum cycle

105

90

80

mA

After one memory cycle,

RAS and CAS high,

VIH = 2.4 V ( TTL)

2

2

2

mA

ICC2

Standby current

After one memory

cycle, RAS and CAS

high

’44400

1

1

1

mA

high,

VIH = VCC – 0.2 V

(CMOS)

’44400P

500

500

500

µA

ICC3

Average refresh current

(RAS only or CBR)

(see Note 4)

VCC = 5.5 V,

Minimum cycle,

RAS cycling,

CAS high (RAS only);

RAS low after CAS low (CBR)

105

90

80

mA

ICC4

Average page

current

(see Notes 3 and 5)

VCC = 5.5 V,

tPC = MIN,

RAS low,

CAS cycling

90

80

70

mA

ICC6†

Self-refresh current

(see Note 3)

CAS

≤ 0.2 V,

RAS < 0.2 V,

tRAS and tCAS > 1000 ms

500

500

500

µA

ICC7

Standby current, outputs

enabled (see Note 3)

RAS = VIH,

CAS = VIL,

Data out = enabled

5

5

5

mA

ICC10†

Battery-backup current

(with CBR)

tRC = 125 µs, tRAS ≤ 1 ms,

VCC – 0.2 V ≤ VIH ≤ 6.5 V,

0 V

≤ VIL ≤ 0.2 V,

W and OE = VIH,

Address and data stable

500

500

500

µA

† For TMS44400P only

NOTES:

3. ICC MAX is specified with no load connected.

4. Measured with a maximum of one address change while RAS = VIL

5. Measured with a maximum of one address change while CAS = VIH