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TMS320VC5409PGE100 Datasheet(PDF) 9 Page - Texas Instruments |
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TMS320VC5409PGE100 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 93 page  Tables 9 April 1999 − Revised October 2008 SPRS082F List of Tables Table Page 2−1 Pin Assignments for the GGU (144-Pin BGA Package) 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 Terminal Functions 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1 Software Wait-State Register (SWWSR) Bit Fields 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2 Software Wait-State Configuration Register (SWCR) Bit Fields 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3 Bank-Switching Control Register Fields 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4 CPU Memory-Mapped Registers 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5 Standard On-Chip ROM Layout 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6 Bus Holder Control Bits 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7 Pin Control Register (PCR) Bit Field Description 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8 Sample Rate Generator Clock Input Options 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9 Sample Rate Generator Register 2 (SRGR2) Bit Field Descriptions 35 . . . . . . . . . . . . . . . . . . . . . . . . . 3−10 McBSP Control Registers and Subaddresses 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11 Clock Mode Settings at Reset 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−12 DMA Interrupts 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−13 DMA Synchronization Events 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−14 DMA Channel Interrupt Selection 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−15 DMA Subbank Addressed Registers 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−16 Peripheral Memory-Mapped Registers 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−17 Interrupt Locations and Priorities 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−18 IFR and IMR Register Bit Fields 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1 Recommended Operating Conditions of Internal Oscillator With External Crystal 52 . . . . . . . . . . . . . 5−2 Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled) Timing Requirements 53 . . . . . . . . . . . . 5−3 Divide-By-Two/Divide-By-Four Clock Option (PLL Disabled) Switching Characteristics 53 . . . . . . . . 5−4 Multiply-By-N Clock Option (PLL Enabled) Timing Requirements 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−5 Multiply-By-N Clock Option (PLL Enabled) Switching Characteristics 54 . . . . . . . . . . . . . . . . . . . . . . . . 5−6 Memory Read Timing Requirements 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−7 Memory Read Switching Characteristics 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−8 Memory Write Switching Characteristics 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−9 Parallel I/O Read Port Timing Requirements 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−10 Parallel I/O Port Read Switching Characteristics 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−11 Parallel I/O Port Write Switching Characteristics 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−12 Ready Timing Requirements for Externally Generated Wait States 61 . . . . . . . . . . . . . . . . . . . . . . . . . 5−13 Ready Switching Characteristics for Externally Generated Wait States 61 . . . . . . . . . . . . . . . . . . . . . . 5−14 HOLD and HOLDA Timing Requirements 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−15 HOLD and HOLDA Switching Characteristics 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−16 Reset, BIO, Interrupt, and MP/MC Timing Requirements 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−17 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics 68 . . . . 5−18 External Flag (XF) and TOUT Switching Characteristics 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−19 McBSP Transmit and Receive Timing Requirements 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−20 McBSP Transmit and Receive Switching Characteristics 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−21 McBSP General-Purpose I/O Timing Requirements 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−22 McBSP General-Purpose I/O Switching Characteristics 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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