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TMS570LS1224 Datasheet(PDF) 4 Page - Texas Instruments |
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TMS570LS1224 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 169 page  HTU1 HTU2 Switched Central Resource Main Cross Bar: Arbitration and Prioritization Control CRC Switched Central Resource Peripheral Central Resource Bridge Dual Cortex-R4F CPUs in Lockstep Switched Central Resource DCAN1 DCAN2 DCAN3 LIN SCI SPI4 64 KB Flash for EEPROM Emulation with ECC MibSPI1 CAN1_RX CAN1_TX CAN2_RX CAN2_TX CAN3_RX CAN3_TX MIBSPI1_CLK MIBSPI1_SIMO[1:0] MIBSPI1_SOMI[1:0] MIBSPI1_nCS[5:0] MIBSPI1_nENA SPI2 SPI2_CLK SPI2_SIMO SPI2_SOMI SPI2_nCS[1:0] SPI2_nENA MibSPI3 MIBSPI3_CLK MIBSPI3_SIMO MIBSPI3_SOMI MIBSPI3_nCS[5:0] MIBSPI3_nENA SPI4_CLK SPI4_SIMO SPI4_SOMI SPI4_nCS0 SPI4_nENA MibSPI5 MIBSPI5_SIMO[3:0] MIBSPI5_SOMI[3:0] MIBSPI5_nCS[3:0] MIBSPI5_nENA LIN_RX LIN_TX SCI_RX SCI_TX IOMM PMM VIM RTI DCC1 DCC2 32K 32K 32K 192kB RAM with ECC DMA POM # 2 # 3 # 5 # 1 # 2 # 1 always on Core/RAM RAM Core Color Legend for Power Domains SYS nPORRST nRST ECLK ESM nERROR 1.25MB Flash with ECC 32K 32K 32K Switched Central Resource I2C N2HET1 GIO N2HET2 MibADC1 MibADC2 EMIF EMIF_CLK EMIF_CKE EMIF_nCS[4:2] EMIF_nCS[0] EMIF_ADDR[12:0] EMIF_BA[1:0] EMIF_DATA[15:0] EMIF_nDQM[1:0] EMIF_nOE EMIF_nWE EMIF_nRAS EMIF_nCAS EMIF_nWAIT eQEP 1,2 eQEPxA eQEPxB eQEPxS eQEPxI eCAP 1..6 eCAP[6:1] ePWM 1..7 nTZ[3:1] SYNCO SYNCI ePWMxA ePWMxB MIBSPI5_CLK TMS570LS1224 SPNS190B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com 1.4 Functional Block Diagram NOTE The block diagram reflects the 337BGA package. Some pins are multiplexed or not available in the 144QFP. For details, see the respective terminal functions tables in Section 4.3. Figure 1-1. Functional Block Diagram 4 Device Overview Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1224 |
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