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TMS320VC5410AZGU12 Datasheet(PDF) 3 Page - Texas Instruments |
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TMS320VC5410AZGU12 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 99 page  Contents TMS320VC5410A Fixed-Point Digital Signal Processor www.ti.com SPRS139I – NOVEMBER 2000 – REVISED OCTOBER 2008 Revision History ........................................................................................................................... 2 1 TMS320VC5410A Features .................................................................................................... 9 2 Introduction ....................................................................................................................... 10 2.1 Description .................................................................................................................. 10 2.2 Terminal/Pin Assignments ................................................................................................ 10 2.2.1 Terminal Assignments for the GGU Package ............................................................... 10 2.2.2 Pin Assignments for the PGE Package ...................................................................... 12 2.3 Signal Descriptions ......................................................................................................... 13 3 Functional Overview ........................................................................................................... 17 3.1 Memory ...................................................................................................................... 17 3.1.1 Data Memory ..................................................................................................... 17 3.1.2 Program Memory ................................................................................................ 18 3.1.3 Extended Program Memory .................................................................................... 18 3.1.4 On-Chip ROM With Bootloader ................................................................................ 18 3.1.5 On-Chip RAM .................................................................................................... 19 3.1.6 On-Chip Memory Security ...................................................................................... 19 3.1.7 Memory Map ..................................................................................................... 20 3.1.7.1 Relocatable Interrupt Vector Table ............................................................... 21 3.2 On-Chip Peripherals ....................................................................................................... 22 3.2.1 Software-Programmable Wait-State Generator ............................................................. 23 3.2.2 Programmable Bank-Switching ................................................................................ 24 3.2.3 Bus Holders ...................................................................................................... 26 3.3 Parallel I/O Ports ........................................................................................................... 26 3.3.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16) ......................................................... 26 3.3.2 HPI Nonmultiplexed Mode ...................................................................................... 27 3.4 Multichannel Buffered Serial Ports (McBSPs) .......................................................................... 29 3.5 Hardware Timer ............................................................................................................ 31 3.6 Clock Generator ............................................................................................................ 32 3.7 Enhanced External Parallel Interface (XIO2) ........................................................................... 34 3.8 DMA Controller ............................................................................................................. 37 3.8.1 Features .......................................................................................................... 37 3.8.2 DMA External Access ........................................................................................... 37 3.8.3 DMPREC Issue ................................................................................................. 38 3.8.4 DMA Memory Map .............................................................................................. 40 3.8.5 DMA Priority Level ............................................................................................... 41 3.8.6 DMA Source/Destination Address Modification ............................................................. 41 3.8.7 DMA in Autoinitialization Mode ................................................................................ 42 3.8.8 DMA Transfer Counting ......................................................................................... 42 3.8.9 DMA Transfer in Doubleword Mode .......................................................................... 42 3.8.10 DMA Channel Index Registers ................................................................................. 43 3.8.11 DMA Interrupts ................................................................................................... 43 3.8.12 DMA Controller Synchronization Events ..................................................................... 44 3.9 General-Purpose I/O Pins ................................................................................................. 45 3.9.1 McBSP Pins as General-Purpose I/O ......................................................................... 45 3.9.2 HPI Data Pins as General-Purpose I/O ...................................................................... 45 3.10 Device ID Register ......................................................................................................... 46 3.11 Memory-Mapped Registers ............................................................................................... 47 3.12 McBSP Control Registers and Subaddresses .......................................................................... 49 3.13 DMA Subbank Addressed Registers .................................................................................... 50 3.14 Interrupts .................................................................................................................... 52 Contents 3 |
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