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TPS70345PWP Datasheet(PDF) 2 Page - Texas Instruments |
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TPS70345PWP Datasheet(HTML) 2 Page - Texas Instruments |
2 / 35 page TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS285A – AUGUST 2000 – REVISED OCTOBER 2002 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) The TPS703xx family of voltage regulators offers very low dropout voltage and dual outputs with power up sequence control, which is designed primarily for DSP applications. These devices have low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 47 µF low ESR capacitors. These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power. Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1 µA at TJ = 25°C. The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (i.e. overload condition) of its regulated voltage, VOUT1 will be turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pullup current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage conditions at VOUT1. The PG1 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 1. The TPS703xx features a RESET (SVS, POR, or power on reset). RESET is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up, RESET goes to a high impedance state (i.e. logic high) after a 120 ms delay when all three of the following conditions are met. First, VIN1 must be above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. Third, VOUT2 must be above approximately 95% of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2. RESET can be used to drive power on reset or a low-battery indicator. If RESET is not used, it can be left floating. Internal bias voltages are powered by VIN1 and require 2.7 V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V. AVAILABLE OPTIONS TJ REGULATOR 1 VO (V) REGULATOR 2 VO (V) TSSOP (PWP) 3.3 V 1.2 V TPS70345PWP 3.3 V 1.5 V TPS70348PWP – 40 °Cto125°C 3.3 V 1.8 V TPS70351PWP – 40 °C to 125°C 3.3 V 2.5 V TPS70358PWP Adjustable (1.22 V to 5.5 V) Adjustable (1.22 V to 5.5 V) TPS70302PWP NOTE: The TPS70302 is programmable using external resistor dividers (see application information) The PWP package is available taped and reeled. Add an R suffix to the device type (e.g., TPS70302PWPR). |
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