NCP1200A

http://onsemi.com

11

DRIVER

PULSES

DRIVER

PULSES

TIME

TIME

TIME

Drv

12 V

10 V

5.4 V

REGULATION

OCCURS

HERE

INTERNAL

FAULT FLAG

FAULT IS

RELAXED

FAULT OCCURS HERE

LATCHOFF

PHASE

STARTUP PHASE

When this level crosses 5.4 V typical, the controller enters

rises toward 12 V and again delivers output pulses at the

its normal operation. Otherwise, a new fault cycle takes

place. Figure 21 shows the evolution of the signals in

presence of a fault.

As the above section describes, the fall down sequence

on the startup sequence of your system, i.e. when you first

apply the power to the IC. The corresponding transient fault

duration due to the output capacitor charging must be less

than the time needed to discharge from 12 V to 10 V,

otherwise the supply will not properly start. The test consists

in either simulating or measuring in the lab how much time

the system takes to reach the regulation at full load. Let’s

fall time of 10 ms could be well appropriated in order to not

trigger the overload detection circuitry. If the corresponding

IC consumption, including the MOSFET drive, establishes

at 1.8 mA for instance, we can calculate the required

t

+ DV @ C

i

, with

DV = 2 V. Then for a wanted Dt of 10 ms, C equals 9 mF or

22

mF for a standard value. When an overload condition

occurs, the IC blocks its internal circuitry and its

consumption drops to 350

mA typical. This happens at

are in latchoff phase. Again, using the calculated 22

mF and

350

mA current consumption, this latchoff phase lasts:

296 ms.