TMS27C210A 65536 BY 16BIT UV ERASABLE

TMS27PC210A 65536 BY 16BIT

PROGRAMMABLE READONLY MEMORIES

SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

3

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Table 2. Operation Modes

MODE†

FUNCTION

READ

OUTPUT

DISABLE

STANDBY

PROGRAMMING

VERIFY

PROGRAM

INHIBIT

SIGNATURE MODE

E

VIL

VIL

VIH

VIL

VIL

VIH

VIL

G

VIL

VIH

X

VIH

VIL

X

VIL

PGM

X

X

X

VIL

VIH

X

X

VPP

VCC

VCC

VCC

VPP

VPP

VPP

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

A9

X

X

X

X

X

X

VH‡

VH‡

A0

X

X

X

X

X

X

VIL

VIH

CODE

DQ0 − DQ15

Data Out

Hi-Z

Hi-Z

Data In

Data Out

Hi-Z

MFG

DEVICE

DQ0 − DQ15

Data Out

Hi-Z

Hi-Z

Data In

Data Out

Hi-Z

97

AB

† X can be VIL or VIH.

‡ VH = 12 V ± 0.5 V.

read / output disable

When the outputs of two or more TMS27C210As or TMS27PC210As are connected in parallel on the same bus,

the output of any particular device in the circuit can be read with no interference from competing outputs of the

other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other

devices in the circuit must have their outputs disabled by applying a high level signal to one of these pins.

latchup immunity

Latchup immunity on the TMS27C210A and TMS27PC210A is a minimum of 250 mA on all inputs and outputs.

This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM

is interfaced to industry standard TTL or MOS logic devices. The input/ output layout approach controls latchup

without compromising performance or packing density.

For more information see application report SMLA001, “Design Considerations; Latchup Immunity of the

HVCMOS EPROM Family”, available through TI Sales Offices.

power down

100

µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.

erasure ( TMS27C210A)

Before programming, the TMS27C210A is erased by exposing the chip through the transparent lid to a high

intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity

×

exposure time) is 15-W

lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state.

Normal ambient light contains the correct wavelength for erasure; therefore, when using the TMS27C210A the

window should be covered with an opaque label.

initializing (TMS27PC210A)

The OTP TMS27PC210A PROM is provided with all bits in the logic high state then logic lows are programmed

into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.