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TMS28F004AXY Datasheet(PDF) 9 Page - Texas Instruments |
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TMS28F004AXY Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 80 page  TMS28F004Axy, TMS28F400Axy 524288 BY 8-BIT/ 262144 BY 16-BIT AUTOSELECT BOOT BLOCK FLASH MEMORIES SMJS829A − JANUARY 1996 − REVISED AUGUST 1997 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 operation Device operations are selected by entering standard JEDEC 8-bit command codes with conventional microprocessor timing into an on-chip CSM through I/O pins DQ0 −DQ7. When the device is powered up, internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation requires a command code to be entered into the CSM. Table 3 lists the CSM codes for all modes of operation. The on-chip status register allows the progress of various operations to be monitored. The status register is interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data on I/O pins DQ0 −DQ7 (cycle 2). Status-register bits SB0 through SB7 correspond to DQ0 through DQ7. Table 3. CSM Codes for Device Mode Selection COMMAND CODE ON DQ0 − DQ7† DEVICE MODE 00h 10h 20h 40h 50h 70h 90h B0h D0h FFh Invalid / Reserved Alternate Program Setup Block-Erase Setup Program Setup Clear Status Register Read Status Register Algorithm Selection Erase-Suspend Erase-Resume/Block-Erase Confirm Read Array † DQ0 is the least significant bit. DQ8 −DQ15 can be any valid 2-state level. command definitions Once a specific command code has been entered, the WSM executes an internal algorithm generating the necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and data for each of the bus cycles. Table 5 lists the status register bits and definitions. Following the read-algorithm-selection-code command, two read cycles are required to access the manufacturer-equivalent code and the device-equivalent code. Table 6, Table 7, and Table 8 list the code. |
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Similar Description - TMS28F004AXY_08 |
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