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TMP816 Datasheet(PDF) 3 Page - Texas Instruments |
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TMP816 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 20 page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OUT2P OUT2N V CC VLIM SENSE RMI VTH CPWM FG RD OUT1P OUT1N SS SGND 6VREG ROFF CT IN+ HB IN– TMP816 www.ti.com SLVS787A – MAY 2009 – REVISED JUNE 2015 5 Pin Configuration and Functions PW Package 20-Pin TSSOP Top View Pin Functions PIN I/O DESCRIPTION NAME NO. OUT2P 1 O Upper-side driver output OUT2N 2 O Lower-side driver output Power supply. For the CM capacitor that is a power stabilization capacitor for PWM drive and for absorption of kickback, the capacitance of 0.1 μF to 1 μF is used. In this device, the lower TR VCC 3 performs current regeneration by switching the upper TR. Connect CM between VCC and GND, with the thick pattern and along the shortest route. Use a Zener diode if kickback causes excessive increase of the supply voltage, because such increase may damage the device. Activates the current limiter when SENSE voltage is higher than VLIM voltage. Connect to VLIM 4 I 6VREG when not used. SENSE 5 I Sense input. Connect to GND when not used. Minimum speed setting. Connect to 6VREG when not used. If device power can be removed RMI 6 I before power is removed from RMI, insert a current limiting resistor to prevent inflow of large current. VTH voltage is generated by filtering the PWM-IN input. If device power can be removed before VTH 7 I power is removed from VTH, insert a current limiting resistor to prevent inflow of large current. Connect to capacitor CP to set the PWM oscillation frequency. With CP = 100 pF, oscillation CPWM 8 O occurs at 25 kHz and provides the basic frequency of PWM. Open collector output, which can detect the rotation speed using the FG output according to the FG 9 O phase shift. Leave open when not used. RD 10 O Open collector output. Outputs low during rotation and high at stop. Leave open when not used. IN– 11 I Hall input HB 12 O This is a Hall element bias, that is, the 1.5-V constant-voltage output. Hall input. Make connecting traces as short as possible to prevent carrying of noise. To futher limit noise, insert a capacitor between IN+ and IN–. The Hall input circuit is a comparator having IN+ 13 I a hysteresis of 20 mV. The application should ensure that the Hall input level more than three times (60 mVp-p) this hysteresis. CT 14 O Lock detection time setting. Capacitor CT is connected. Sets the soft switching time to cut the reactive current before phase change. Connect to 6VREG ROFF 15 I when not used. 6VREG 16 O 6-V regulator output SGND 17 Connected to the control circuit power supply system. Connect to soft-start setting capacitor. Connect the capacitor between 6VREG and SS. Enables SS 18 O setting of the soft-start time according to the capacity of the capacitor (see Figure 3 and Figure 4). Connect to ground if not used. OUT1N 19 O Lower-side driver output OUT1P 20 O Upper-side driver output Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TMP816 |
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