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TMDS3260050 Datasheet(PDF) 10 Page - Texas Instruments |
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TMDS3260050 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 44 page  TMS320C511A DIGITAL SIGNAL PROCESSOR SPRS053 – FEBRUARY 1997 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory The ’C511A implements three separate address spaces for program memory, data memory, and input/output (I/O). Each space accommodates a total of 64K 16-bit words (see Figure 1). Within the 64K words of data space, the 256 to 32K words at the top of the address range can be defined to be external global memory in increments of powers of two, as specified by the contents of the global-memory allocation register (GREG). Access to global memory is arbitrated using the global memory bus request (BR) signal. The ’C511A device includes a considerable amount of on-chip memory to aid in system performance and integration including ROM and dual-access RAM (DARAM). Refer to Table 1 for the amount and types of memory available on this device. On the ’C511A, the first 96 (0 – 5Fh) data-memory locations are allocated for memory-mapped registers. This memory-mapped register space contains various control and status registers including those for the CPU, serial port, timer, and software wait-state generators. Additionally, the first 16 I/O port locations are mapped into this data-memory space, allowing them to be accessed either as data memory using single-word instructions or as I/O locations with two-word instructions. Two-word instructions allow access to the full 64K words of I/O space. The ’C511A contains 24K words of mask-programmable on-chip ROM located in program memory space. This ROM can be programmed with contents unique to to any particular application. The ROM is enabled or disabled by the state of the MP/ MC control input upon resetting the device or by manipulating the MP/ MC bit in the PMST status register after reset. The ROM occupies the first 24K words of internal program space (0 – 5FFFh) when enabled (which is the lowest block of program memory). When disabled, these addresses are located in the device’s external program-memory space. The ’C511A also has a mask-programmable option that provides security protection for the contents of on-chip ROM. When this internal option bit is programmed, no externally-originating instruction can access the on-chip ROM. This feature can be used to provide security for proprietary algorithms. The ’C511A also provides a total of 1 056 16-bit words of on-chip data RAM, divided into three separate blocks: block 0 (B0), block 1 (B1), and block 2 (B2). Of the 1 056 words, 544 words (blocks B1 and B2) are always data memory and 512 words (block B0) are programmable as either data or program memory. A data-memory size of 1056 words allows the ’C511A to handle a data array of 1 024 words (512 words if on-chip RAM is used for program memory) while still leaving 32 locations for intermediate storage. When using block B0 as program memory, instructions can be downloaded from external program memory into on-chip RAM and then executed. The CLRC CNF (configure block B0 as data memory) and SETC CNF (configure block B0 as program memory) instructions allow dynamic configuration of the memory maps through software. Regardless of the configuration, code still can be executed from external program memory. When using on-chip RAM, ROM, or high-speed external memory, the ’C511A runs at full speed with no wait states. The ability of the DARAM to allow two accesses to be performed in one cycle, coupled with the parallel nature of the ’C511A architecture, enables the device to perform three concurrent memory accesses in any given machine cycle. Externally, the READY line can be used to interface the ’C511A to slower, less expensive external memory. Downloading programs from slow off-chip memory to on-chip RAM can speed processing while cutting system costs. |
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