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TMS320F28050PNQ Datasheet(PDF) 3 Page - Texas Instruments |
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TMS320F28050PNQ Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 150 page  M0 SARAM 1Kx16 (0-wait) 16-bit Peripheral Bus M1 SARAM 1Kx16 (0-wait) SCI-A, B C (4L FIFO) SCI- , SCI- ePWM1–ePWM7 SPI-A (4L FIFO) I2C-A (4L FIFO) 32-Bit Peripheral Bus GPIO MUX C28x CPU (60 MHz) PIE (up to 96 interrupts) CPU Timer 0 CPU Timer 1 CPU Timer 2 TRST TCK TDI TMS TDO OSC1, OSC2, Ext, PLL, LPM, WD X2 32-bit Peripheral Bus (CLA-accessible) GPIO Mux LPM Wakeup CLA + Message RAMs ADC 0-wait Result Regs Boot ROM 12Kx16 (0-wait) Non-Secure L0 SARAM (2Kx16) (0-wait, Secure) CLA Data RAM2 COMP + Digital Filter COMPAn COMPBn eCAN-A (32-mbox) eCAP eQEP X1 GPIO MUX Program- mable Gain Amps VREG POR/ BOR Memory Bus Secure ROM (A) 2Kx16 (0-wait) Secure L1 DPSARAM (1Kx16) (0-wait, Secure) CLA Data RAM0 L2 DPSARAM (1Kx16) (0-wait, Secure) CLA Data RAM1 L3 DPSARAM (4Kx16) (0-wait, Secure) CLA Program RAM CLA Data ROM (4Kx16) CTRIPnOUT ADC 3.75 MSPS 32-bit Peripheral Bus (CLA-accessible) XRS GPIO Mux XCLKIN 3 External Interrupts Memory Bus PSWD Dual- Zone Security Module + ECSL OTP/Flash Wrapper Z1/Z2 User OTP Secure PUMP FLASH 28055, 28054: 64K x 16, 10 Sectors 28053, 28052, 28051: 32K x 16, 5 Sectors 28050: 16K x 16, 3 Sectors Secure TMS320F28055, TMS320F28054, TMS320F28053 TMS320F28052, TMS320F28051, TMS320F28050 www.ti.com SPRS797B – NOVEMBER 2012 – REVISED JULY 2014 1.4 Functional Block Diagram Figure 1-1 shows a functional block diagram of the device. A. Stores Secure Copy Code Functions on all devices. B. Not all peripheral pins are available at the same time due to multiplexing. Figure 1-1. Functional Block Diagram Copyright © 2012–2014, Texas Instruments Incorporated Device Overview 3 Submit Documentation Feedback Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 |
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